
APPENDIX E SUMMARY OF PRECAUTIONS
S1C33E07 TECHNICAL MANUAL
EPSON
AP-E-5
AP
Notes
The contents of all RTC interrupt control bits are indeterminate when power is turned on, and are not
initialized to specific values by initial reset.
After power-on, be sure to set RTCIEN (D0/0x301904) to 0 (interrupt disabled) for preventing the occurrence
of unwanted RTC interrupts. Also be sure to write 1 to RTCIRQ (D0/0x301900) to reset it.
RTCIEN: RTC Interrupt Enable Bit in the RTC Interrupt Mode Register (D0/0x301904)
RTCIRQ: Interrupt Status Bit in the RTC Interrupt Status Register (D0/0x301900)
Immediately after the OSC1 oscillator circuit is activated (as at power-on), a finite time (of about 3 seconds)
is required for OSC1 oscillation to stabilize. Do not let the RTC start counting until this time elapses.
Misc Registers
The Misc registers at addresses 0x300010–0x30001A are write-protected. Before the Misc registers can
be rewritten, write protection of these registers must be removed by writing data 0x96 to the Misc Protect
Register (0x300020). Note that since unnecessary rewrites to addresses 0x300010–0x30001A could lead to
erratic system operation, the Misc Protect Register (0x300020) should be set to other than 0x96 unless said
Misc registers must be rewritten.
The control bits shown below are used to control clock supply to the Misc registers. Be aware that different
control bits are provided for two address ranges.
0x300010–0x300020: MISC_HCKE (D24/0x301B04)
0x300C41–0x300C4D: EGPIO_MISC_CKE (D12/0x301B04)
For details of each control bits, see Section III.1, “Clock Management Unit (CMU).”
The low-drive control bit is disabled when the pin is used as the general-purpose I/O port (Pxx).
If the bus signals are forcibly driven low when the CPU is running by the instructions fetched from an
external memory, the CPU will not be able to run after that point. To drive the signals low, the CPU must be
running with the program stored in the internal RAM.
16-Bit Timers (T16)
When setting the count clock or operation mode, make sure the 16-bit timer is turned off.
If a same value is set to the comparison data A and B registers, a hazard may be generated in the output
signal. Therefore, do not set the comparison registers as A = B.
There is no problem when the interrupt function only is used.
When using the output clock, set the comparison data registers as A
≥ 0 and B ≥ 1. The minimum settings are
A = 0 and B = 1. In this case, the timer output clock cycle is the input clock
× 1/2.
When the comparison data registers are set as A
> B in normal mode, no comparison A interrupt is generated.
In this case, the output signal is fixed at the off level.
In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A
> 2 × B
+ 1.
After an initial reset, the cause-of-interrupt flag becomes indeterminate. To prevent generation of an
unwanted interrupt or IDMA request, be sure to reset this flag and register in the software.
To prevent another interrupt from being generated by the same cause of interrupt after an interrupt has
occurred, be sure to reset the cause-of-interrupt flag before setting the PSR again or executing the reti
instruction.
Watchdog Timer (WDT)
When NMI or reset signal output by the watchdog timer is enabled, the watchdog timer must be reset within
the set NMI/reset generation cycle.
Do not set a value equal to or less than 0x0000001F in the comparison data register.