
II BUS MODULES: INTELLIGENT DMA (IDMA)
II-2-8
EPSON
S1C33E07 TECHNICAL MANUAL
II.2.3 IDMA Invocation
The triggers by which IDMA is invoked have the following three causes:
1. Cause of interrupt in internal peripheral circuits (hardware trigger)
2. Trigger in the software application
3. Link setting
Enabling/disabling DMA transfer
The IDMA controller is enabled by writing 1 to the IDMA enable bit IDMAEN (D0/0x301105), and is ready to
accept the triggers described above. However, before enabling a DMA transfer, be sure to set the base address
and the control information for the channel to be invoked correctly. If IDMAEN (D0/0x301105) is set to 0, no
IDMA invocation request is accepted.
IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x301105)
IDMA invocation by a cause of interrupt in internal peripheral circuits
Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by a cause
of interrupt in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are
predetermined. The relationship between the causes of interrupt that have this function and the IDMA channels
is shown in Table II.2.3.1.
Table II.2.3.1 Interrupt Causes Used to Invoke IDMA
Peripheral circuit
I/O ports
High-speed DMA
16-bit timers 0–5
Serial interface
Ch.0–Ch.1
A/D converter
I/O ports
LCDC
Serial interface
Ch.2
SPI
I/O ports
or port MUX interrupt
I/O ports
I2S
Cause of interrupt
Port input 0
Port input 1
Port input 2
Port input 3
Ch.0, end of transfer
Ch.1, end of transfer
Timer 0 comparison B
Timer 0 comparison A
Timer 1 comparison B
Timer 1 comparison A
Timer 2 comparison B
Timer 2 comparison A
Timer 3 comparison B
Timer 3 comparison A
Timer 4 comparison B
Timer 4 comparison A
Timer 5 comparison B
Timer 5 comparison A
Ch.0 receive buffer full
Ch.0 transmit buffer empty
Ch.1 receive buffer full
Ch.1 transmit buffer empty
End of A/D conversion
Port input 4
Port input 5
Port input 6
Port input 7
End of frame
Ch.2 receive buffer full
Ch.2 transmit buffer empty
Receive DMA request
Transmit DMA request
Port input 8 / SPI
Port input 9 / USB PDREQ
Port input 10 / USB INT
Port input 11 / DCSIO
Port input 12
Port input 13
Port input 14
Port input 15
I2S
IDMA enable bit
DEP0 (D0/0x300294)
DEP1 (D1/0x300294)
DEP2 (D2/0x300294)
DEP3 (D3/0x300294)
DEHDM0 (D4/0x300294)
DEHDM1 (D5/0x300294)
DE16TU0 (D6/0x300294)
DE16TC0 (D7/0x300294)
DE16TU1 (D0/0x300295)
DE16TC1 (D1/0x300295)
DE16TU2 (D2/0x300295)
DE16TC2 (D3/0x300295)
DE16TU3 (D4/0x300295)
DE16TC3 (D5/0x300295)
DE16TU4 (D6/0x300295)
DE16TC4 (D7/0x300295)
DE16TU5 (D0/0x300296)
DE16TC5 (D1/0x300296)
DESRX0 (D6/0x300296)
DESTX0 (D7/0x300296)
DESRX1 (D0/0x300297)
DESTX1 (D1/0x300297)
DEADE (D2/0x300297)
DEP4 (D4/0x300297)
DEP5 (D5/0x300297)
DEP6 (D6/0x300297)
DEP7 (D7/0x300297)
DELCDC (D1/0x30029C)
DESRX2 (D2/0x30029C)
DESTX2 (D3/0x30029C)
DESPIRX (D4/0x30029C)
DESPITX (D5/0x30029C)
DEP8 (D0/0x3002AE)
DEP9 (D1/0x3002AE)
DEP10 (D2/0x3002AE)
DEP11 (D3/0x3002AE)
DEP12 (D4/0x3002AE)
DEP13 (D5/0x3002AE)
DEP14 (D6/0x3002AE)
DEP15 (D7/0x3002AE)
DEI2S (D0/0x3002AF)
IDMA request bit
RP0 (D0/0x300290)
RP1 (D1/0x300290)
RP2 (D2/0x300290)
RP3 (D3/0x300290)
RHDM0 (D4/0x300290)
RHDM1 (D5/0x300290)
R16TU0 (D6/0x300290)
R16TC0 (D7/0x300290)
R16TU1 (D0/0x300291)
R16TC1 (D1/0x300291)
R16TU2 (D2/0x300291)
R16TC2 (D3/0x300291)
R16TU3 (D4/0x300291)
R16TC3 (D5/0x300291)
R16TU4 (D6/0x300291)
R16TC4 (D7/0x300291)
R16TU5 (D0/0x300292)
R16TC5 (D1/0x300292)
RSRX0 (D6/0x300292)
RSTX0 (D7/0x300292)
RSRX1 (D0/0x300293)
RSTX1 (D1/0x300293)
RADE (D2/0x300293)
RP4 (D4/0x300293)
RP5 (D5/0x300293)
RP6 (D6/0x300293)
RP7 (D7/0x300293)
RLCDC (D1/0x30029B)
RSRX2 (D2/0x30029B)
RSTX2 (D3/0x30029B)
RSPIRX (D4/0x30029B)
RSPITX (D5/0x30029B)
RP8 (D0/0x3002AC)
RP9 (D1/0x3002AC)
RP10 (D2/0x3002AC)
RP11 (D3/0x3002AC)
RP12 (D4/0x3002AC)
RP13 (D5/0x3002AC)
RP14 (D6/0x3002AC)
RP15 (D7/0x3002AC)
RI2S (D0/0x3002AD)
IDMA Ch.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41
42
43
44
45
46