
VI PERIPHERAL MODULES 4 (PORTS): GENERAL-PURPOSE I/O PORTS (GPIO)
S1C33E07 TECHNICAL MANUAL
EPSON
VI-1-7
VI
GPIO
Since P00 is masked from interrupt by SMPK00 (D0/0x3003D4), no interrupt occurs at that point (2) above.
Next, because P03 becomes 0 at (3), an interrupt is generated due to the lack of a match between the data of the
input pin P0[4:1] that is enabled for interrupt and that of the input comparison register SCPK0[4:1] (D[4:1]/
0x3003D2).
Since only a change in states in which the input data and the content of SCPKx (D[4:0]/0x3003D2, D[3:0]/
0x3003D3) become unmatched after being matched constitutes an interrupt generation condition as described
above, no interrupt is generated when a change in states from one unmatched state to another, as in (4), occurs.
Consequently, if another interrupt is to be generated again following the occurrence of an interrupt, the state of
the input pin must be temporarily restored to the same content as that of SCPKx, or SCPKx must be set again.
Note that the input pins masked from interrupt by SMPKx (D[4:0]/0x3003D4, D[3:0]/0x3003D5) do not affect
interrupt generation conditions.
An interrupt is generated for FPK1 in the same way as described above.
VI.1.4.3 Control Registers of the Interrupt Controller
Table VI.1.4.3.1 shows the control registers of the interrupt controller that are provided for each input-interrupt sys-
tem.
Table VI.1.4.3.1 Control Registers of Interrupt Controller
System
FPT15
FPT14
FPT13
FPT12
FPT11
FPT10
FPT9
FPT8
FPT7
FPT6
FPT5
FPT4
FPT3
FPT2
FPT1
FPT0
FPK1
FPK0
Cause-of-interrupt flag
FP15(D7/0x3002A9)
FP14(D6/0x3002A9)
FP13(D5/0x3002A9)
FP12(D4/0x3002A9)
FP11(D3/0x3002A9)
FP10(D2/0x3002A9)
FP9(D1/0x3002A9)
FP8(D0/0x3002A9)
FP7(D6/0x300287)
FP6(D5/0x300287)
FP5(D4/0x300287)
FP4(D3/0x300287)
FP3(D3/0x300280)
FP2(D2/0x300280)
FP1(D1/0x300280)
FP0(D0/0x300280)
FK1(D5/0x300280)
FK0(D4/0x300280)
Interrupt priority register
PP15L[2:0](D[6:4]/0x3002A3)
PP14L[2:0](D[2:0]/0x3002A3)
PP13L[2:0](D[6:4]/0x3002A2)
PP12L[2:0](D[2:0]/0x3002A2)
PP11L[2:0](D[6:4]/0x3002A1)
PP10L[2:0](D[2:0]/0x3002A1)
PP9L[2:0](D[6:4]/0x3002A0)
PP8L[2:0](D[2:0]/0x3002A0)
PP7L[2:0](D[6:4]/0x30026D)
PP6L[2:0](D[2:0]/0x30026D)
PP5L[2:0](D[6:4]/0x30026C)
PP4L[2:0](D[2:0]/0x30026C)
PP3L[2:0](D[6:4]/0x300261)
PP2L[2:0](D[2:0]/0x300261)
PP1L[2:0](D[6:4]/0x300260)
PP0L[2:0](D[2:0]/0x300260)
PK1L[2:0](D[6:4]/0x300262)
PK0L[2:0](D[2:0]/0x300262)
Interrupt enable register
EP15(D7/0x3002A6)
EP14(D6/0x3002A6)
EP13(D5/0x3002A6)
EP12(D4/0x3002A6)
EP11(D3/0x3002A6)
EP10(D2/0x3002A6)
EP9(D1/0x3002A6)
EP8(D0/0x3002A6)
EP7(D6/0x300277)
EP6(D5/0x300277)
EP5(D4/0x300277)
EP4(D3/0x300277)
EP3(D3/0x300270)
EP2(D2/0x300270)
EP1(D1/0x300270)
EP0(D0/0x300270)
EK1(D5/0x300270)
EK0(D4/0x300270)
When the interrupt generation condition described above is met, the corresponding cause-of-interrupt flag is set to 1.
If the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated.
Interrupts due to a cause of interrupt can be disabled by leaving the interrupt enable register bit for that cause of
interrupt set to 0. The cause-of-interrupt flag is set to 1 whenever interrupt generation conditions are met, regardless
of the setting of the interrupt enable register.
The interrupt priority register sets the interrupt priority level (0 to 7) for each interrupt system. An interrupt request
to the CPU is accepted only when no other interrupt request of a higher priority has been generated.
In addition, only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the input
interrupt level set using the interrupt priority register will the input interrupt request actually be accepted by the
CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer
to Section III.2, “Interrupt Controller (ITC).”