VI PERIPHERAL MODULES 4 (PORTS): GENERAL-PURPOSE I/O PORTS (GPIO)
VI-1-6
EPSON
S1C33E07 TECHNICAL MANUAL
Selecting input pins
For the FPK1 interrupt system, a four-bit input pin group (two input pins when using P8[5:4]) can be selected
from the eight predefined groups. For the FPK0 system, a five-bit input pin group can be selected.
Table VI.1.4.2.1 shows the control bits and the selectable groups for each cause of interrupt.
Table VI.1.4.2.1 Selecting Pins for Key Input Interrupts
Cause of
interrupt
FPK1
FPK0
111
P9[7:4]
P9[4:0]
Control bit
SPPK1[2:0] (D[6:4]) Key input interrupt select
SPPK0[2:0] (D[2:0]) register (0x3003D0)
110
P8[5:4]
P8[4:0]
101
P7[3:0]
P5[4:0]
100
P6[7:4]
P6[4:0]
011
P3[3:0]
P4[4:0]
010
P2[7:4]
P2[4:0]
001
P1[7:4]
P1[4:0]
000
P0[7:4]
P0[4:0]
SPPK settings
Conditions for key input-interrupt generation
The key input interrupt circuit has the input mask bits SMPK0[4:0] (D[4:0]/0x3003D4) for FPK0 and
SMPK1[3:0] (D[3:0]/0x3003D5) for FPK1, and the input comparison bits SCPK0[4:0] (D[4:0]/0x3003D2) for
FPK0 and SCPK1[3:0] (D[3:0]/0x3003D3) for FPK1 to set input-interrupt conditions.
SMPK0[4:0]: FPK0 Input Mask Bits in the Key Input Interrupt (FPK0) Input Mask Register (D[4:0]/0x3003D4)
SMPK1[3:0]: FPK1 Input Mask Bits in the Key Input Interrupt (FPK1) Input Mask Register (D[3:0]/0x3003D5)
SCPK0[4:0]: FPK0 Input Comparison Bits in the Key Input Interrupt (FPK0) Input Comparison Register
(D[4:0]/0x3003D2)
SCPK1[3:0]: FPK1 Input Comparison Bits in the Key Input Interrupt (FPK1) Input Comparison Register
(D[3:0]/0x3003D3)
The input mask bit (SMPK) is used to mask the input pin that is not used for an interrupt. This bit masks each
input pin, whereas the interrupt enable bit of the interrupt controller masks the cause of interrupt for each inter-
rupt group.
The input comparison bit (SCPK) is used to select whether an interrupt for each input port is to be generated at
the rising or falling edge of the input.
A change in state occurs so that the input pin enabled for interrupt by the interrupt mask bit (SMPK) and the
content of the input comparison bit (SCPK) become unmatched after being matched, the cause-of-interrupt flag
(FK) is set to 1 and, if other interrupt conditions are met, an interrupt is generated.
Figure VI.1.4.2.2 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the P0[4:0] pins
are selected for the input-pin group and the control register of the interrupt controller is set so as to enable gen-
eration of a FPK0 interrupt.
Input mask register SMPK0
Input comparison register SCPK0
SMPK04
1
SMPK03
1
SMPK02
1
SMPK01
1
SMPK00
0
Input port P0
(1)
(Initial value)
Interrupt generation
P04
1
SCPK04
1
SCPK03
1
SCPK02
0
SCPK01
1
SCPK00
0
With the settings shown above, FPK0 interrupt is generated under the condition shown below.
(2)
P04
1
(3)
P04
1
(4)
P04
1
P03
1
P02
0
P01
1
P00
0
P03
1
P02
0
P01
1
P00
1
P03
0
P02
0
P01
1
P00
0
P03
0
P02
1
P01
1
P00
0
Because interrupt has been disabled for
P00, an interrupt will be generated when
non-conformity occurs between the
contents of the four bits P01–P04 and the
four input comparison bits SCPK0[4:1].
Figure VI.1.4.2.2 FPK0 Interrupt Generation Example (when P0[4:0] is selected by SPPK0[2:0])