
I S1C33E07 SPECIFICATIONS: PIN DESCRIPTION
I-3-6
EPSON
S1C33E07 TECHNICAL MANUAL
I/O
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I
(Hi-Z)
I
(Hi-Z)
I
(Hi-Z)
I
(Hi-Z)
I
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
Pull-
up/down
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
Function
P33:
General-purpose I/O port (default)
CARD5:
Card I/F signal 5 output
#DMAREQ3: HSDMA Ch.3 request input
P60:
General-purpose I/O port (default)
SIN2:
Serial I/F Ch.2 data input
DCSIO0:
DCSIO port
EXCL0:
16-bit timer 0 event counter input
P61:
General-purpose I/O port (default)
SOUT2:
Serial I/F Ch.2 data output
DCSIO1:
DCSIO port
EXCL1:
16-bit timer 1 event counter input
P62:
General-purpose I/O port (default)
#SCLK2:
Serial I/F Ch.2 clock input/output
#ADTRG:
A/D converter trigger input
CMU_CLK: CMU external clock output
P63:
General-purpose I/O port (default)
#SRDY2:
Serial I/F Ch.2 ready input/output
WDT_CLK: Watchdog timer clock output
#WDT_NMI: Watchdog timer NMI signal output
P64:
General-purpose I/O port (default)
#WAIT:
Wait cycle request input
EXCL2:
16-bit timer 2 event counter input
P65:
General-purpose I/O port (default)
SDI:
SPI data input
FPDAT8:
LCD data
P66:
General-purpose I/O port (default)
SDO:
SPI data output
FPDAT9:
LCD data
P67:
General-purpose I/O port (default)
SPI_CLK:
SPI clock
FPDAT10:
LCD data
P70:
General-purpose I/O port (default)
AIN0:
A/D converter Ch.0 input
P71:
General-purpose I/O port (default)
AIN1:
A/D converter Ch.1 input
P72:
General-purpose I/O port (default)
AIN2:
A/D converter Ch.2 input
P73:
General-purpose I/O port (default)
AIN3:
A/D converter Ch.3 input
P74:
General-purpose I/O port (default)
AIN4:
A/D converter Ch.4 input
EXCL5:
16-bit timer 5 event counter input
P80:
General-purpose I/O port (default)
FPFRAME: LCD frame clock output
P81:
General-purpose I/O port (default)
FPLINE:
LCD line clock output
P82:
General-purpose I/O port (default)
FPSHIFT:
LCD shift clock output
P83:
General-purpose I/O port (default)
FPDRDY:
LCD DRDY/MOD signal output
TFT_CTL1: LCDC TFT I/F control signal 1 output
BCLK:
Bus clock output
P84:
General-purpose I/O port (default)
DCSIO0:
DCSIO port
FPDAT11:
LCD data
P85:
General-purpose I/O port (default)
DCSIO1:
DCSIO port
P90:
General-purpose I/O port (default)
FPDAT0:
LCD data
P91:
General-purpose I/O port (default)
FPDAT1:
LCD data
P92:
General-purpose I/O port (default)
FPDAT2:
LCD data
P93:
General-purpose I/O port (default)
FPDAT3:
LCD data
P94:
General-purpose I/O port (default)
FPDAT4:
LCD data
QFP
11
77
78
79
80
34
35
36
37
52
51
50
49
48
53
54
55
56
57
58
63
64
65
66
68
Pin No.
Pin name
P33
CARD5
#DMAREQ3
P60
SIN2
DCSIO0
EXCL0
P61
SOUT2
DCSIO1
EXCL1
P62
#SCLK2
#ADTRG
CMU_CLK
P63
#SRDY2
WDT_CLK
#WDT_NMI
P64
#WAIT
EXCL2
P65
SDI
FPDAT8
P66
SDO
FPDAT9
P67
SPI_CLK
FPDAT10
P70
AIN0
P71
AIN1
P72
AIN2
P73
AIN3
P74
AIN4
EXCL5
P80
FPFRAME
P81
FPLINE
P82
FPSHIFT
P83
FPDRDY
TFT_CTL1
BCLK
P84
DCSIO0
FPDAT11
P85
DCSIO1
P90
FPDAT0
P91
FPDAT1
P92
FPDAT2
P93
FPDAT3
P94
FPDAT4
PFBGA
E1
L13
K12
J12
K14
K3
M2
M3
N1
N6
M6
N7
M5
N5
P7
L6
L7
M7
L8
M8
L10
L11
P10
M10
M11