
I S1C33E07 SPECIFICATIONS: PIN DESCRIPTION
S1C33E07 TECHNICAL MANUAL
EPSON
I-3-7
I
Pin
I/O
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(Hi-Z)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
I/o
(PU)
Pull-
up/down
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
100k PU
1
Function
P95:
General-purpose I/O port (default)
FPDAT5:
LCD data
P96:
General-purpose I/O port (default)
FPDAT6:
LCD data
P97:
General-purpose I/O port (default)
FPDAT7:
LCD data
PA0:
Extended general-purpose I/O port (default)
TFT_CTL0: LCDC TFT I/F control signal 0 output
PA1:
Extended general-purpose I/O port (default)
FPDAT8:
LCD data
TFT_CTL0: LCDC TFT I/F control signal 0 output
PA2:
Extended general-purpose I/O port (default)
FPDAT9:
LCD data
TFT_CTL1: LCDC TFT I/F control signal 1 output
PA3:
Extended general-purpose I/O port (default)
FPDAT10:
LCD data
TFT_CTL2: LCDC TFT I/F control signal 2 output
CARD0:
Card I/F signal 0 output
PA4:
Extended general-purpose I/O port (default)
FPDAT11:
LCD data
TFT_CTL3: LCDC TFT I/F control signal 3 output
CARD1:
Card I/F signal 1 output
PB0:
Extended general-purpose I/O port (default)
FPDAT8:
LCD data
I2S_SDO:
I2S send data signal
CARD2:
Card I/F signal 2 output
PB1:
Extended general-purpose I/O port (default)
FPDAT9:
LCD data
I2S_WS:
I2S word select signal
CARD3:
Card I/F signal 3 output
PB2:
Extended general-purpose I/O port (default)
FPDAT10:
LCD data
I2S_SCK:
I2S serial clock signal
CARD4:
Card I/F signal 4 output
PB3:
Extended general-purpose I/O port (default)
FPDAT11:
LCD data
I2S_MCLK: I2S master clock signal
CARD5:
Card I/F signal 5 output
QFP
69
70
71
–
Pin No.
Pin name
P95
FPDAT5
P96
FPDAT6
P97
FPDAT7
PA0
TFT_CTL0
PA1
FPDAT8
TFT_CTL0
PA2
FPDAT9
TFT_CTL1
PA3
FPDAT10
TFT_CTL2
CARD0
PA4
FPDAT11
TFT_CTL3
CARD1
PB0
FPDAT8
I2S_SDO
CARD2
PB1
FPDAT9
I2S_WS
CARD3
PB2
FPDAT10
I2S_SCK
CARD4
PB3
FPDAT11
I2S_MCLK
CARD5
PFBGA
N10
N12
M12
P11
N11
L12
P12
P13
L2
L4
L3
M1
Table I.3.2.5 USB Interface Pin List
I/O
I/o
I
Pull-
up/down
–
Function
USB D+ pin
USB D- pin
USB VBUS pin. Allows input of 5 V
QFP
75
74
76
Pin No.
Pin name
USBDP
USBDM
USBVBUS
PFBGA
M14
N14
L14
Table I.3.2.6 Other Pin List
I/O
I
I/o
i/
O
(H)
i/
O
(L)
I
Pull-
up/down
50k PU
100k PU
–
50k PD
60k PD
Function
Initial reset input pin (with noise reduction circuit)
NMI request input pin (with noise reduction circuit)
DSIO: Serial input/output for debugging (with noise reduction circuit) (default)
P34:
General-purpose I/O port
DCLK: DCLK signal output for debugging (default)
P35:
General-purpose I/O port
DST2: DST2 signal output for debugging (default)
P36:
General-purpose I/O port
Boot mode select signal 1 input
Boot mode select signal 0 input
Wafer level burn-in test enable input
TEST-0 input
QFP
72
73
31
33
32
46
–
45
Pin No.
Pin name
#RESET
#NMI
DSIO
P34
DCLK
P35
DST2
P36
BOOT1
BOOT0
BURNIN
TEST0
PFBGA
N13
M13
K1
L1
K4
L5
K13
M9
M4