I S1C33E07 SPECIFICATIONS: CPU CORE AND BUS ARCHITECTURE
S1C33E07 TECHNICAL MANUAL
EPSON
I-5-3
I
CPU
I.5.3 Instruction Set
The C33 PE Core instruction set consists of the function-extended instruction set of the C33 STD Core CPU and
the new instructions, in addition to the conventional S1C33-series instructions. Some instructions of the C33 STD
Core CPU are deleted. As the C33 PE Core is object-code compatible with the C33 STD Core CPU, software assets
can be transported from the S1C33 series to the C33 PE model easily, with minimal modifications required.
All of the instruction codes are fixed to 16 bits in length which, combined with pipelined processing, allows most
important instructions to be executed in one cycle. For details, refer to the “S1C33 Family C33 PE Core Manual.”
Table I.5.3.1 S1C33-Series-Compatible Instructions
Classification
Arithmetic operation
Branch
Function
Addition between general-purpose registers
Addition of a general-purpose register and immediate
Addition of SP and immediate (with immediate zero-extended)
Addition with carry between general-purpose registers
Subtraction between general-purpose registers
Subtraction of general-purpose register and immediate
Subtraction of SP and immediate (with immediate zero-extended)
Subtraction with carry between general-purpose registers
Arithmetic comparison between general-purpose registers
Arithmetic comparison of general-purpose register and immediate
(with immediate zero-extended)
Signed integer multiplication (16 bits
× 16 bits → 32 bits)
Unsigned integer multiplication (16 bits
× 16 bits → 32 bits)
Signed integer multiplication (32 bits
× 32 bits → 64 bits)
Unsigned integer multiplication (32 bits
× 32 bits → 64 bits)
PC relative conditional jump
Branch condition: !Z & !(N ^ V)
Delayed branching possible
PC relative conditional jump
Branch condition: !(N ^ V)
Delayed branching possible
PC relative conditional jump
Branch condition: N ^ V
Delayed branching possible
PC relative conditional jump
Branch condition: Z | N ^ V
Delayed branching possible
PC relative conditional jump
Branch condition: !Z & !C
Delayed branching possible
PC relative conditional jump
Branch condition: !C
Delayed branching possible
PC relative conditional jump
Branch condition: C
Delayed branching possible
PC relative conditional jump
Branch condition: Z | C
Delayed branching possible
PC relative conditional jump
Branch condition: Z
Delayed branching possible
PC relative conditional jump
Branch condition: !Z
Delayed branching possible
PC relative jump
Delayed branching possible
Absolute jump
Delayed branching possible
PC relative subroutine call
Delayed call possible
Absolute subroutine call
Delayed call possible
Subroutine return
Delayed return possible
Return from interrupt or exception handling
Return from the debug processing routine
Software exception
Debug exception
add
adc
sub
sbc
cmp
mlt.h
mltu.h
mlt.w
mltu.w
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
jp
jp.d
call
call.d
ret
ret.d
reti
retd
int
brk
%rd,%rs
%rd,imm6
%sp,imm10
%rd,%rs
%rd,imm6
%sp,imm10
%rd,%rs
%rd,sign6
%rd,%rs
sign8
%rb
sign8
%rb
imm2
Mnemonic