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| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 101/210頁 |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
101
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Facility Data Link (FDL)
(continued)
Receive HDLC Mode
This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC
frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO.
The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the
receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of
n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received
HDLC frame are not stored in the receive FIFO. When receiving ANSI PRM frames, the frame check sequence
bytes are stored in the receive FIFO.
The SF byte has the following format.
Table 54. Receive Status of Frame Byte
RSF B7
BAD CRC
RSF B6
ABORT
RSF B5
RFIFO
OVERRUN
RSF B4
BAD BYTE
COUNT
RSF B3
0
RSF B2
0
RSF B1
0
RSF B0
0
Bit 7 of the SF status byte is the CRC status bit. A 1
indicates that an incorrect CRC was detected. A 0 indi-
cates the CRC is correct. Bit 6 of the SF status byte is
the abort status. A 1 indicates the frame associated
with this status byte was aborted (i.e., the abort
sequence was detected after an opening flag and
before a subsequent closing flag). An abort can also
cause bits 7 and/or 4 to be set to 1. An abort is not
reported when a flag is followed by seven ones. Bit 5 is
the FIFO overrun bit. A 1 indicates that a receive FIFO
overrun occurred (the 64-byte FIFO size was
exceeded). Bit 4 is the FIFO bad byte count that indi-
cates whether or not the bit count received was a multi-
ple of eight (i.e., an integer number of bytes). A 1
indicates that the bit count received after 0-bit deletion
was not a multiple of eight, and a 0 indicates that the bit
count was a multiple of eight. When a nonbyte-aligned
frame is received, all bits received are present in the
receive FIFO. The byte before the SF status byte con-
tains less than eight valid data bits. The HDLC block
provides no indication of how many of the bits in the
byte are valid. User application programming controls
processing of nonbyte-aligned frames. Bit 3—bit 0 of
the SF status byte are not used and are set to 0. A
good frame is implied when the SF status byte is
00 (hex).
Receive FDL FIFO
Whenever an SF byte is present in the receive FIFO,
the end of frame registers FDL_SR0 bit 4 (FREOF) and
FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue
status (register FDL_SR2 bit 0—bit 6) bits report the
number of bytes up to and including the first SF byte. If
no SF byte is present in the receive FIFO, the count
directly reflects the number of data bytes available to
be read. Depending on the FDL frame size, it is possi-
ble for multiple frames to be present in the receive
FIFO. The receive fill level indicator register FDL_PR6
bit 0—bit 5 (FRIL) can be programmed to tailor the ser-
vice time interval to the system. The receive FIFO full
register FDL_SR0 bit 3 (FRF) interrupt is set in the
interrupt status register when the receive FIFO reaches
the preprogrammed full position. An FREOF interrupt is
also issued when the receiver has identified the end of
frame and has written the SF byte for that frame. An
FDL overrun interrupt register FDL_SR0 bit 5
(FROVERUN) is generated when the receiver needs to
write either status or data to the receive FIFO while the
receive FIFO is full. An overrun condition will cause the
last byte of the receive FIFO to be overwritten with an
SF byte indicating the overrun status. A receive idle
register FDL_SR0 bit 6 (FRIDL) interrupt is issued
whenever 15 or more continuous ones have been
detected.
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