Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
24
L Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions-Global
(continued)
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.
Pin
Symbol
Type
*
Description
100
RDY_DTACK
O
monitoring.
101
MPCK
I
u
102
JTAGTDO
O
103
JTAGTDI
I
u
104
JTAGTCK
I
u
105
JTAGTMS
I
u
106
JTAGTRST
I
d
107
WR_DS
I
110
SECOND
O
* I
u
indicates an internal pull-up. I
d
indicates an internal pull-down.
Ready.
In the Intelinterface mode, this pin is asserted high to
indicate the completion of a read or write access; this pin is forced
into a high-impedance state while CS is high.
Data Transfer Acknowledge (Active-Low).
In the Motorola
interface mode, DTACK is asserted low to indicate the completion
of a read or write access; DTACK is 1 otherwise.
Microprocessor Clock.
Microprocessor clock used in the Intel
mode to generate the READY signal.
JTAG Data Output.
Serial output data sampled on the falling edge
of TCK from the boundary-scan test circuitry.
JTAG Data Input.
Serial input data sampled on the rising edge of
TCK for the boundary-scan test circuitry.
JTAG Clock Input.
TCK provides the clock for the boundary-scan
test logic.
JTAG Mode Select (Active-High).
The signal values received at
TMS are sampled on the rising edge of TCK and decoded by the
boundary-scan TAP controller to control boundary-scan test opera-
tions.
JTAG Reset Input (Active-Low).
Assert this pin low to asynchro-
nously initialize/reset the boundary-scan test logic.
Write (Active-Low).
In the Intel mode, the value present on the
data bus is latched into the addressed register on the positive edge
of the signal applied to WR.
Data Strobe (Active-Low).
In the Motorolamode, when AS is low
and R/W is low (write), the value present on the data bus is latched
into the addressed register on the positive edge of the signal
applied to DS; when AS is low and R/W is high (read), the T7630
drives the data bus with the contents of the addressed register
while DS is low.
Second Pulse.
A one second timer with an active-high pulse. The
duration of the pulse is one RLCK cycle. The received line clock of
FRAMER1 (RLCK1) is the default clock source for the internal sec-
ond pulse timer. When LOFRMCLK1 is active, the received line
clock of FRAMER2 is used as the clock signal source for the inter-
nal second pulse timer. The second pulse is used for performance