參數(shù)資料
型號(hào)： T7630
英文描述： T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
中文描述： T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）
文件頁(yè)數(shù)： 9/210頁(yè)
文件大小： 3075K
代理商： T7630
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Lucent Technologies Inc.
9
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents
(continued)
Table
Page
Table 98. CRC Error Counter Registers (FRM_SR12—FRM_SR13) ((60C—60D); (C0C—C0D))......................157
Table 99. E-Bit Counter Registers (FRM_SR14—FRM_SR15) ((60E—60F); (C0E—C0F))................................157
Table 100. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) ((610—611);
(C10—C11)) .......................................................................................................................................................157
Table 101. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13)) ...................157
Table 102. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15)) ......................158
Table 103. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) ((616—617); (C16—C17))...........158
Table 104. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) ((618—619); (C18—C19))........158
Table 105. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) ((61A—61B); (C1A—C1B))..............158
Table 106. ET-RE Errored Seconds Counter (FRM_SR28—FRM_SR29) ((61C—61D); (C1C—C1D)) ..............158
Table 107. ET-RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) ((61E—61F); (C1E—C1F)) ....158
Table 108. ET-RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) ((620—621); (C20—C21))..158
Table 109. ET-RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23))..........159
Table 110. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25))....................159
Table 111. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) ((626—627); (C26—C27)).........159
Table 112. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) ((628—629); (C28—C29)) .....159
Table 113. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) ((62A—62B); (C2A—C2B))............159
Table 114. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) ((62C—62D); (C2C—C2D))............159
Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) ((62E—62F); (C2E—C2F))..159
Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49 ((630—631);
(C30—C31)) .......................................................................................................................................................160
Table 117. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) ((632—633); (C32—C33)) .......160
Table 118. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34).................................................................160
Table 119. Receive Sa Register (FRM_SR53) (635; C35)...................................................................................160
Table 120. SLC-96 FDL Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F)) ........................161
Table 121. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F)) .............................161
Table 122. Transmit Framer ANSI Performance Report Message Status Register Structure ..............................162
Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) ((640—658);
(C40—C58)) .......................................................................................................................................................162
Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) ((640—65F);
(C40—C5F)).......................................................................................................................................................162
Table 125. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) ((660—667);
(C60—C67)) .......................................................................................................................................................163
Table 126. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60).....................................................164
Table 127. Interrupt Enable Register (FRM_PR1) (661; C61)..............................................................................165
Table 128. Interrupt Enable Register (FRM_PR2) (662; C62)..............................................................................165
Table 129. Interrupt Enable Register (FRM_PR3) (663; C63)..............................................................................165
Table 130. Interrupt Enable Register (FRM_PR4) (664; C64)..............................................................................165
Table 131. Interrupt Enable Register (FRM_PR5) (665; C65)..............................................................................165
Table 132. Interrupt Enable Register (FRM_PR6) (666; C66)..............................................................................165
Table 133. Interrupt Enable Register (FRM_PR7) (667; C67)..............................................................................165
Table 134. Framer Mode Bits Decoding (FRM_PR8) (668; C68).........................................................................166
Table 135. Line Code Option Bits Decoding (FRM_PR8) (668; C68) ..................................................................166
Table 136. CRC Option Bits Decoding (FRM_PR9) (669, C69)...........................................................................167
Table 137. Alarm Filter Register (FRM_PR10) (66A; C6A)..................................................................................167
Table 138. Errored Event Threshold Definition.....................................................................................................168
Table 139. Errored Second Threshold Register (FRM_PR11) (66B; C6B) ..........................................................168
Table 140. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) ((66C—66D;
C6C—C6D)) .......................................................................................................................................................168
Table 141. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E)...........................................................169
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PDF描述
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