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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 23/210頁(yè) |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
23
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Pin Information
(continued)
Table 2. Pin Descriptions-Global
* I
u
indicates an internal pull-up. I
d
indicates an internal pull-down.
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.
Pin
Symbol
Type
*
I
u
Description
74
MPMODE
MPMODE.
Strap to ground to enable the Motorola 68360 microprocessor
protocol (MODE1 or MODE2).
Strapped to V
DD
to enable the Intel80X86/88
microprocessor protocol (MODE3 or MODE4).
Read (Active-Low).
In the Intelinterface mode, the T7630 drives the data
bus with the contents of the addressed register while RD is low.
Read/Write. In the Motorola interface mode, this signal is asserted high for
read accesses; this pin is asserted low for write accesses.
MPMUX.
Strap to V
SS
to enable the demultiplexed address and data bus
mode. Strap to V
DD
to enable the multiplexed address and data bus mode.
Chip Select (Active-Low).
In the Intelinterface mode, this pin must be
asserted low to initiate a read or write access and kept low for the duration of
the access; asserting CS low forces RDY out of its high-impedance state into
a 0 state.
Address Latch Enable/Address Strobe.
In the address/data bus multiplex
mode of the microprocessor, when this signal transitions from high to low, the
state of the address bus is latched into internal address registers. In the
demultiplexed address mode, the address is transparent through the T7630
and is latched on the rising edge of the ALE_AS signal. Alternatively, if
ALE_AS is not connected to the micropressor or other driver, it must be con-
nected to ground.
Microprocessor Address_Data Bus.
Multiplexed address and bidirectional
data bus used for read and write accesses. High-impedance output.
Microprocessor Address Bus.
Address bus used to access the internal reg-
isters.
Interrupt.
INTERRUPT is asserted high indicating an internal interrupt condi-
tion/event has been generated. Otherwise, INTERRUPT is 0. Interrupt
events/conditions are maskable through the control registers. Interrupt asser-
tion may be inverted (active-low) by setting register GREG 4 bit 6 = 1. This
output may not be wire OR connected to any other logic output.
75
RD_R/W
I
76
MPMUX
I
u
77
CS
I
78
ALE_AS
I
79—86
AD0—AD7
I/O
87—98
A0—A11
I
99
INTERRUPT
O
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| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
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