Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
186
L Lucent Technologies Inc.
Framer Register Architecture
(continued)
CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64)
These four registers define which receive CHI highway RCHIDATA or RCHIDATAB contains valid data for the active
time slot. A 0 enables RCHIDATA, and a 1 enables RCHIDATAB. The default value of these registers is 00 (hex).
Table 175. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0))
CHI Transmit Control Register (FRM_PR65)
The default value of this register is 00 (hex).
Table 176. CHI Transmit Control Register (FRM_PR65) (6A1; CA1)
CHI Receive Control Register (FRM_PR66)
The default value of this register is 00 (hex).
Table 177. CHI Receive Control Register (FRM_PR66) (6A2; CA2)
Reserved Parameter/Control Registers
Registers FRM_PR67 and FRM_PR68, addresses 6A3 and 6A4 or CA3 and CA4, are reserved. Write these regis-
ters to 0.
Register
FRM_PR61
FRM_PR62
FRM_PR63
FRM_PR64
Bit
7—0
7—0
7—0
7—0
Symbol
Description
RHS31—RHS24
RHS23—RHS16
RHS15—RHS8
RHS7—RHS0
Receive Highway Select Bits 31—24.
Receive Highway Select Bits 23—16.
Receive Highway Select Bits 15—8.
Receive Highway Select Bits 7—0.
Bit
0
Symbol
TBYOFF6
Description
Transmit CHI 64-Byte Offset.
A 1 enables a 64-byte offset from TCHIFS to the begin-
ning of the next transmit CHI frame on TCHIDATA. A 0 enables a 0-byte offset (if bit 0—
bit 5 of FRM_PR47 = 0). Combing bit 0—bit 5 of FRM_PR47 with this bit allows program-
ming the byte offset from 0—127.
Transmit CHI Double Time-Slot Mode.
A 1 enables the transmit CHI double time-slot
mode. In this mode, the TCHI clock runs at twice the rate of TCHIDATA.
Reserved.
Write to 0.
1
TCHIDTS
2—7
—
Bit
0
Symbol
RBYOFF6
Description
Receive CHI 64-Byte Offset.
A 1 enables a 64-byte offset from RCHIFS to the begin-
ning of the next receive CHI frame on RCHIDATA. A 0 enables a 0-byte offset (if bit 0—
bit 5 of FRM_PR48 = 0). Combing bit 0—bit 5 of FRM_PR48 with this bit allows program-
ming the byte offset from 0—127.
Receive CHI Double Time-Slot Mode.
A 1 enables the transmit CHI double time-slot
mode. In this mode, the RCHI clock runs at twice the rate of RCHIDATA.
Reserved.
Write to 0.
1
RCHIDTS
2—7
—