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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 19/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
19
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Pin Information
(continued)
Table 1 and Table 2 show the list of T7630 pins and a functional description for each.
Table 1. Pin Descriptions-Channel 1 and Channel 2
* I
u
indicates an internal pull-up.
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.
Pin
Symbol
Type
*
Description
CH1 CH2
1, 36, 73,
109
2
GRND
P
Digital Ground Reference.
38
LOFRMRLCK
O
Loss of Framer Receive Line Clock.
This pin is asserted high (1) when the
framer internal receive line clock does not toggle for a 250
μ
s interval. Once
asserted, this signal is deasserted on the first edge of the framer internal
receive line clock.
Terminator Mode: (FRAMER, pin 41/141 = 1) LOFRMRLCK is asserted high
when SYSCK clock, pin 3/35, is absent.
Framer Mode: (FRAMER, pin 41/141 = 0) LOFRMRLCK is asserted high
when RLCK clock, pin 47/135, is absent.
LIU System Clock.
The clock signal used for clock and data recovery and jit-
ter attenuation. This clock must be ungapped and free of jitter. For CKSEL =
1, a 16x clock (for DS1, SYSCK = 24.704 MHz ± 100 ppm and for CEPT,
SYSCK = 32.768 MHz ± 100 ppm). For CKSEL = 0, a 1x clock (for DS1,
SYSCK = 1.544 MHz ± 100 ppm and for CEPT, SYSCK = 2.048 MHz
± 100 ppm).
Error Phase-Lock Loop Signal.
The error signal proportional to the phase
difference between DIV-PLLCK and DIV-RCHICK as detected by the internal
PLL circuitry (refer to the Phase-Lock Loop Circuit section).
Divided-Down RCHI Clock.
32 kHz or 8 kHz clock signal derived from the
RCHICK input signal.
Divided-Down PLLCK Clock.
32 kHz or 8 kHz clock signal derived from the
PLLCK input signal.
Transmit Framer Phase-Locked Line Interface Clock.
Clock signal used to
time the transmit framer. This signal must be phase-locked to RCHICK clock
signal and be ungapped and free of jitter. For FRM_PR45, bit 0 (HFLF) = 0, in
DS1 PLLCK = 1.544 MHz and in CEPT PLLCK = 2.048 MHz. For
FRM_PR45, bit 0 (HFLF) = 1 in DS1 PLLCK = 6.176 MHz and in CEPT
PLLCK = 8.192 MHz.
Analog Ground Reference.
No Connection.
3
35
SYSCK
I
u
4
34
PLLCK-EPLL
O
5
33
DIV-RCHICK
O
6
32
DIV-PLLCK
O
7
31
PLLCK
I
8
30
GRND
A
NC
P
—
9, 12, 19,
26, 29
10
28
RRING_RND
I
Receive Bipolar Ring.
Negative bipolar input data from the receive analog
line isolation transformer.
Receive Negative Rail Data.
Valid when the FRAMER pin is strapped to 0 V.
Nonreturn-to-zero (NRZ) serial data latched by the rising edge of RLCK. Data
rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. In the single-rail mode, when
RND = 1 the receive bipolar violation counter increments once for each rising
edge of RLCK.
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