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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 149/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
149
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture
(continued)
On all 16-bit counter registers (FRM_SR8—FRM_SR51), both bytes are cleared only after reading both bytes.
These status registers are two byte register pairs. These register pairs must be read in succession, with the lower
byte read first followed by a read of higher byte. Once a read is initiated on one of the bytes, the updating of that
counter is disabled and remains disabled until both bytes are read. All events during this interval are lost. Updating
of the counter registers is stopped when all of the bits are set to 1. Updating resumes after the registers are cleared
on read. These register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be
followed immediately by a read of the remaining byte of the pair.
Status registers FRM_SR0—FRM_SR63 are clear-on-read (COR) registers. These registers are cleared by the
framer internal received line clock (RFRMCK). At least two RFRMCK cycles (1.3 μs for DS1 and 1.0 μs for CEPT)
must be allowed between successive reads of the same COR register to allow it to properly clear.
Framer Status/Counter Registers
Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read only registers.
Interrupt Status Register (FRM_SR0)
The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in reg-
isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1.
Table 88. Interrupt Status Register (FRM_SR0) (600; C00)
Bit
0
1
2
Symbol
FAC
RAC
FAE
Description
Facility Alarm Condition.
A 1 indicates a facility alarm occurred (go read FRM_SR1).
Remote Alarm Condition.
A 1 indicates a remote alarm occurred (go read FRM_SR2).
Facility Alarm Event.
A 1 indicates a facility alarm occurred (go read FRM_SR3 and
FRM_SR4).
Errored Second Event.
A 1 indicates an errored second event occurred (go read
FRM_SR5, FRM_SR6, and FRM_SR7).
Transmit Signaling Superframe Event.
A 1 indicates that a MOS superframe block
has been transmitted and the transmit signaling data buffers are ready for new data.
Receive Signaling Superframe Event.
A 1 indicates that a MOS superframe block has
been received and the receive signaling data buffers must be read.
Reserved.
SLC-96 Stack Ready.
A 1 indicates that either the transmit framer SLC-96 stack is
ready for more data or the receive framer SLC-96 stack contains new data.
3
ESE
4
TSSFE
5
RSSFE
6
7
—
S96SR
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| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
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