- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T7630 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) PDF資料下載
參數(shù)資料
| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 15/210頁 |
| 文件大小： | 3075K |
| 代理商： | T7630 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁
Lucent Technologies Inc.
Lucent Technologies Inc.
15
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Functional Description
(continued)
The Lucent T7630 Dual T1/E1 Terminator (Terminator-
II) provides two complete T1/E1 interfaces each con-
sisting of a fully integrated, full-featured, short-haul line
interface transceiver and a full-featured primary rate
framer with an HDLC formatter for facility data link
access. The T7630 provides glueless interconnection
from a T1 or E1 analog line interface to devices inter-
facing to its CHI; for example, the T7270 Time-Slot
Interchanger or T7115A Synchronous Protocol Data
Formatter.
The line interface receiver performs clock and data
recovery using a digital phase-locked loop, thereby
avoiding false lock conditions that are common when
recovering sparse data patterns with an analog imple-
mentation. The receiver’s equalization circuit guaran-
tees a high level of interference immunity. The receive
line unit monitors the amplitude at the receive input for
analog loss of signal (ALOS) detection and the pulse
density of the receive signal for digital loss of signal
(DLOS) detection. The receive line unit may be pro-
grammed to detect bipolar violations. The line interface
unit may be optionally bypassed. It is recommended
that the LIU/framer interface be placed in dual-rail
mode, which allows the framers error/event detector to
detect and report code and bipolar violation (BPV)
errors.
The line interface unit’s transmit equalization is done
with low-impedance output drivers that provide shaped
waveforms to the transformer, guaranteeing template
conformance. The transmitter will interface to the digital
cross connect (DSX) at lengths up to 655 feet for DS1
operation, and line impedances of 75
or 120
for
CEPT-E1 operation. The transmit line unit monitors
nonfunctional links due to faults at the primary of the
transmit transformer and periods of no data transmis-
sion.
The line codes supported in the framer unit include
AMI, T1 B8ZS, per-channel T1 zero code suppression
and ITU-CEPT HDB3.
The T7630 supports T1 D4, T1DM, and SLC-96 SF,
ESF; ITU-CEPT-E1 basic frame; ITU-CEPT-E1 time
slot 0 multiframe; and time slot 16 multiframe formats.
The receive framer monitors the following alarms: loss
of receive clock, loss of frame, alarm indication signal
(AIS), remote frame alarms, and remote multiframe
alarms. These alarms are detected as defined by the
appropriate ANSI, AT&T, and ITUstandards.
Performance monitoring as specified by AT&T, ANSI,
and ITU is provided through counters monitoring bipo-
lar violation, frame bit errors, CRC errors, CEPT E bit =
0 conditions, CEPT Sa6 codes, errored events, errored
seconds, bursty errored seconds, severely errored sec-
onds, and unavailable seconds.
In-band loopback activation and deactivation codes
can be transmitted to the line via the payload or the
facility data link. In-band loopback activation and deac-
tivation codes in the payload or the facility data link are
detected.
System, payload, and line loopbacks are programma-
ble.
The default system interface is a 2.048 Mbits/s data
and 2.048 MHz clock CHI serial bus. This CHI interface
consists of independent transmit and receive paths.
The CHI interface can be reconfigured into several
modes: a 2.048 Mbits/s data interface and 4.096 MHz
clock interface, a 4.096 Mbits/s data interface and
4.096 MHz clock interface, a 4.096 Mbits/s data inter-
face and 8.192 MHz clock interface, a 8.192 Mbits/s
data interface and 8.192 MHz clock interface, and
8.192 Mbits/s data interface and 16.384 MHz clock
interface.
The signaling formats supported are T1 per-channel
robbed-bit signaling (RBS), channel-24 message-ori-
ented signaling (MOS), and ITU-CEPT-E1 channel-
associated signaling (CAS). In the T1, RBS mode voice
and data channels are programmable. The entire pay-
load can be programmed into a data-only (no signaling
channels) mode, i.e., transparent mode. Signaling
access can be through the on-chip signaling registers
or the system CHI port in the associated signaling
mode. Data and its associated signaling information
can be accessed through the CHI in either DS1 or
CEPT-E1 modes.
Extraction and insertion of the facility data link in ESF,
T1DM, SLC-96, or CEPT-E1 modes are provided
through a four-port serial interface or through a micro-
processor-accessed, 64-byte FIFO either with HDLC
formatting or transparently. In the T7630’s SLC-96 or
CEPT-E1 frame formats, a facility data link (FDL) is pro-
vided for FDL access. The bit-oriented ESF data-link
messages defined in ANSI T1.403-1995 are monitored
by the receive framer’s facility data link unit and are
transmitted by the transmit framer FDL
The receive framer includes a two-frame elastic store
buffer for jitter attenuations that performs control slips
and provides indication of slip directions.
Accessing internal registers is done via the demulti-
plexed/multiplexed address and data bus microproces-
sor interface using either the Intel 80188 (or 80X88)
interface protocol with independent read and write sig-
nals or the Motorola MC680X0 or M68360 interface
protocol with address and data strobe signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| T8100A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8102A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7630426 | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #2450 3/8 Spring Snap Link Stainless Steel UPC Tagged |
| T-7630-TL2-DB | 制造商:Legerity 功能描述:5V DUAL T1/E1 SHORT-HAUL TERMINATOR |
| T7633 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Dual T1/E1 3.3 V Short-Haul Terminator |
| T7645036 | 功能描述:手工工具 Campbell Snap Link #2450, 7/16", Steel RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool |
| T7645106 | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #7350 1/8 Quick Link Steel Zinc Plated UPC Tagged |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。