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參數(shù)資料
| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 191/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
191
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
FDL Parameter/Control Registers (800—80E; E00—E0E)
These registers define the mode configuration of each framer unit. These registers are initially set to a default value
upon a hardware reset. These registers are all read/write registers.
Default states of all bits in this register group are also indicated in the parameter/control register map.
Table 183. FDL Configuration Control Register (FDL_PR0) (800; E00)
* The FRANSIT bits (FDL_PR0 bits 4—7) must be changed only following an FDL reset or when the FDL is idle.
Table 184. FDL Control Register (FDL_PR1) (801; E01)
Bit
0
Symbol
FDINT
Description
Dynamic Interrupt.
FDINT = 0 causes multiple occurrences of the same event to gener-
ate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0.
FDINT = 1 causes multiple interrupts to be generated. This bit should normally be set to
0.
Flags.
FLAGS = 0 forces the transmission of the idle pattern (11111111) in the absence
of transmit FDL information. FLAGS = 1 forces the transmission of the flag pattern
(01111110) in the absence of transmit FDL information. This bit resets to 0.
Reserved.
Write to 0.
Receive ANSI Bit Code Threshold.
These bits define the number of ESF ANSIbit
codes needed for indicating a valid code. The default is ten (1010 (binary))*.
1
FLAGS
2—3
4—7
—
FRANSIT0—
FRANSIT3
Bit
0
Symbol
FRLB
Description
Remote Loopback.
FRLB = 1 loops the received facility data back to the transmit facility
data interface. This bit resets to 0.
Local Loopback.
FLLB = 1 loops transmit facility data back to the receive facility data
link interface. The receive facility data link information from the framer interface is
ignored. This bit resets to 0.
FDL Receiver Enable.
FRE = 1 activates the FDL receiver. FRE = 0 forces the FDL
receiver into an inactive state. This bit resets to 0.
FDL Transmitter Enable.
FTE = 1 activates the FDL transmitter. FTE = 0 forces the FDL
transmitter into an inactive state. This bit resets to 0.
FDL Receiver Reset.
FRR = 1 generates an internal pulse that resets the FDL receiver.
The FDL receiver FIFO and related circuitry are cleared. The FREOF, FRF, FRIDL, and
OVERRUN interrupts are cleared. This bit resets to 0.
FDL Transmitter Reset.
FTR = 1 generates an internal pulse that resets the FDL trans-
mitter. The FDL transmit FIFO and related circuitry are cleared. The FTUNDABT bit is
cleared, and the FTEM interrupt is set; the FTDONE bit is forced to 0 in the HDLC mode
and forced to 1 in the transparent mode. This bit resets to 0.
FDL Receive PRM Frames.
FRPF = 1 allows the receive FDL unit to write the entire
receive performance report message including the frame header and CRC data into the
receive FDL FIFO. This bit resets to 0.
Transmit PRM Enable.
When this bit is set, the receive framer will write into the transmit
FDL FIFO its performance report message data. The current second of this data is
stored in the receive framer’s status registers. The receive framer’s PRM is transmitted
once per second. The PRM is followed by either idles or flags transmitted after the PRM.
When this bit is 0, the transmit FDL expects data from the microprocessor interface.
1
FLLB
2
FRE
3
FTE
4
FRR
5
FTR
6
FRPF
7
FTPRM
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