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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 22/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
22
L Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions-Channel 1 and Channel 2
(continued)
* I
u
indicates an internal pull-up.
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.
Pin
Symbol
Type
*
Description
CH1 CH2
124
58
TCHIDATA
O
Transmit CHI Data.
Serial output system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance
state for all inactive time slots.
Transmit CHI Data B.
Serial output system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance
state for all inactive time slots.
Divided-Down Receive Line Clock.
8 kHz clock signal derived from the
recovered receive line interface unit clock or the RLCK input signal.
Divided-Down CHI Clock.
8 kHz clock signal derived from the transmit CHI
CLOCK input signal.
Error Phase-Lock Loop Signal.
The error signal proportional to the phase
difference between DIV-TCHICK and DIV-RLCK as detected from the internal
PLL circuitry (refer to the Phase-Lock Loop Circuit section.
Transmit Framer Frame Sync.
This signal is the 8 kHz frame synchroniza-
tion pulse in the transmit framer. This signal is active-high.
Transmit Framer Signaling Superframe Sync.
This signal is the CEPT
signaling superframe (multiframe) synchronization pulse in the transmit
framer. This signal is active-high.
Transmit Framer CRC-4 Multiframe Sync.
This signal is the CEPT CRC-4
submultiframe synchronization pulse in the transmit framer. This signal is
active-high.
Transmit Facility Data Link Clock.
In DS1-DDS with data link access, this is
an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame latches data link
bits on the falling edge of TFDLCK.
Transmit Facility Data Link.
Optional serial input facility data link bit stream
inserted into the transmit line data stream by the transmit framer. In DS1-
DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In
the CEPT frame format, TFDL can be programmed to one of the Sa bits of
the NOT-FAS frame time slot 0.
Receive CHI Clock.
2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
This clock must be free of jitter.
Receive CHI Frame Sync.
Receive CHI 8 kHz frame synchronization pulse
phase-locked to RCHICK.
Receive CHI Data.
Serial input system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s.
Receive CHI Data B.
Serial input system data at 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s.
123
59
TCHIDATAB
O
122
60
DIV-RLCK
O
121
61
DIV-TCHICK
O
120
62
TCHICK-EPLL
O
119
63
TFS
O
118
64
TSSFS
O
117
65
TCRCMFS
O
116
66
TFDLCK
O
115
67
TFDL
I
114
68
RCHICK
I
113
69
RCHIFS
I
112
70
RCHIDATA
I
111
71
RCHIDATAB
I
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PDF描述 |
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| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
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| T8102A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8105A | H.100/H.110 Interface and Time-Slot Interchangers |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
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