參數(shù)資料
型號(hào): T7630
英文描述: T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
中文描述: T7630雙T1/E1的5.0V的短途終結(jié)者(終結(jié)者-Ⅱ)
文件頁(yè)數(shù): 97/210頁(yè)
文件大?。?/td> 3075K
代理商: T7630
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Lucent Technologies Inc.
Lucent Technologies Inc.
97
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL)
Data may be extracted from and inserted into the facility data link in SLC-96, DDS, ESF, and CEPT framing for-
mats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register FRM_PR43
bit 0—bit 2. Access to the FDL is made through:
I
The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 28 shows the timing of these signals.
I
The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC section may
beframed in HDLC format or passed through transparently
.
t8
5-3910(F).cr.1
Figure 44. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections
In the ESF frame format, automatic assembly and transmission of the performance report message (PRM) as
defined in both ANSIT1.403-1995 and Bellcore’s TR-TSY-000194 Issue 1, 12—87 is managed by the receive
framer and transmit FDL sections. The ANSIT1.403-1995 bit-oriented data link messages (BOM) can be transmit-
ted by the transmit FDL section and recognized and stored by the receive FDL section.
Receive Facility Data Link Interface
Summary
A brief summary of the receive facility data link functions is given below:
I
Bit-oriented message (BOM) operation.
The ANSIT1.403-1995 bit-oriented data link messages are recog-
nized and stored in register FDL_SR3. The number of times that an ANSI code must be received for detection
can be programmed from 1 to 10 by writing to register FDL_PR0 bit 4— bit 7. When a valid ANSIcode is
detected, register FDL_SR0 bit 7 (FRANSI) is set.
I
HDLC operation.
This is the default mode of operation when the FDL receiver is enabled (register FDL_PR1 bit
2 = 1). The HDLC framer detects the HDLC flags, checks the CRC bytes, and stores the data in the FDL receiver
FIFO (register FDL_SR4) along with a status of frame (SF) byte.
I
HDLC operation with performance report messages (PRM).
This mode is enabled by setting register
FDL_PR1 bit 2 and bit 6 to 1. In this case, the receive FDL will store the 13 bytes of the PRM report field in the
FDL receive FIFO (register FDL_SR4) along with a status of frame (SF) byte.
t9
t9
t10
t11
t8: TFDLCK CYCLE =
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10: RFDLCK CYCLE =
t11: RFDLCK TO RFDL DELAY = 40 ns
TFDLCK
TFDL
RFDLCK
RFDL
250
μ
s (ALL OTHER
MODES)
125
μ
s (DDS)
250
μ
s (ALL OTHER
MODES)
125
μ
s (DDS)
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