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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 145/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
145
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Control Registers
The bits in the control registers allow the user to configure the various device functions for the individual line inter-
face channels 1 and 2. All the control bits (with the exception of LOSSTD) are active-high.
LIU Control Register (LIU_REG2)
Table 79. LIU Control Register (LIU_REG2) (402, A02)
LIU Control Register (LIU_REG3)
The default value of this register is E4 (hex)
Table 80. LIU Control Register (LIU_REG3) (403, A03).
Note: These registers must be written to 1 for the LIU-to-framer interface to be functional.
Bit
0
1
2
Symbol
—
—
LOSSTD
Description
Reserved.
Write to 0.
Reserved.
Write to 0.
The LOSSTD bit selects the conformance protocol for the DLOS receiver alarm
function. LOSSTD = 0 selects standards T1M1.3/93-005, ITU-T G.755 for DS1
mode and ITU-T G.755 for CEPT mode. LOSSTD = 1 selects standards TR-TSY-
000009 for DS1 and ITU-T G.775 for CEPT.
Reserved.
Write to 0.
The HIGHZ bit places the LIU in a high-impedance state. When HIGHZ = 1, the
TTIP and TRING transmit drivers for the specified channel are placed in a high-
impedance state.
The RESTART bit is used for device initialization through the microprocessor inter-
face. RESTART = 1 resets the data path circuits. Data path circuits will be reset, but
the microprocessor registers state will not be altered by a restart action.
Reserved.
Write to 0.
3
4
—
HIGHZ
5
RESTART
6—7
—
Bit
0
Symbol
JAR
Description
The JAR bit is used to enable and disable the jitter attenuator function in the receive
path. The JAR and JAT control bits are mutually exclusive, i.e., either JAR or the JAT
control bit can be set, but not both. JAR = 1 places jitter attenuator in the receive path.
The JAT bit is used to enable and disable the jitter attenuator function in the transmit
path. The JAT and JAR control bits are mutually exclusive, i.e., either JAT or the JAR
control bit can be set, but not both. JAT = 1 places jitter attenuator in the transmit path.
The CODE bit is used to enable and disable the B8ZS/HDB3 zero substitution coding
in the transmit and decoding in the receive path. CODE is used in conjunction with the
DUAL bit and is valid only for single-rail operation. CODE = 1 activates the coding/
decoding functions. The default value is CODE = 1.
The DUAL bit is used to select single- or dual-rail mode of operation. DUAL = 1 selects
the dual-rail mode.
The LOSSD bit selects the shutdown function for the receiver during DLOS. LOSSD
operates in conjunction with the RCVAIS bit (see Table 4, LOSSD and RCVAIS Control
Configurations (Not Valid During Loopback Modes), repeated below for reference)
Reserved. Write to 1.
1
JAT
2
CODE
3
DUAL
4
LOSSD
5—7
—
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| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
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