Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
148
L Lucent Technologies Inc.
Line Interface Control Registers
(continued)
Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 7)
* In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.
In CEPT mode, equalization is specified for coaxial or twisted-pair cable.
Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0.
Loss measured at 772 kHz.
§ In 75
applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same trans-
former as in CEPT 120
applications (see Line Interface Unit: Line Circuitry section).
Framer Register Architecture
REGBANK3 and REGBANK6 contain the status and programmable control registers for the framer and system
(CHI) interface channels FRM1 and FRM2. The base address for REGBANK3 is 600 (hex) and for REGBANK6 is
C00 (hex). Within these register banks, the bit map is identical for both FRM1 and FRM2.
The framer registers are structures as shown in Table 87. Default values are given in the individual register defini-
tion tables.
Table 87. Framer Status and Control Blocks Address Range (Hexadecimal)
The complete register map for the framer is given in Table 201 to Table 203.
All status registers are clocked with the internal framer receive line clock (RFRMCK).
Bits in status registers FRM_SR1 and FRM_SR7 are set at the onset of the condition and are cleared on read
when the given condition is no longer present. These registers can generate interrupts if the corresponding register
bits are enabled in interrupt enable registers FRM_PR0—FRM_PR7.
Short-Haul Applications
EQ2
EQ1
EQ0
Service
Clock Rate
Transmitter Equalization
*
Maximum
Cable Loss
to DSX
Feet
Meters
dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DSX-1
1.544 MHz
0 to 131
131 to 262
262 to 393
393 to 524
524 to 655
0 to 40
40 to 80
80 to 120
120 to 160
160 to 200
0.6
1.2
1.8
2.4
3.0
—
CEPT
§
2.048 MHz
75
(Option 2)
120
or 75
(Option 1)
Not Used
Framer Register Block
Status Registers (COR) ((600—63F); (C00—C3F))
Receive Signaling Registers ((640—65F); (C40—C5F))
Parameter (Configuration) Registers ((660—6A6); (C60—CA6))
Transmit Signaling Registers ((6E0—6FF); (CE0—CFF))