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| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 42/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
42
L Lucent Technologies Inc.
Line Interface Unit: Other Features
(continued)
LIU Delay Values
The transmit coder has 5 UI delay whether it is in the
path or not and whether it is B8ZS or HDB3. Its delay is
only removed when in single-rail mode. The remainder
of the transmit path has 4.6 UI delay. The receive
decoder has five UI delay whether it is in the path or not
and whether it is B8ZS or HDB3. Its delay is only
removed when in single-rail mode or CDR = 0. The
equalizer plus slicer delay is nearly 0 UI delay. The jitter
attenuator delay is nominally 33 UI but can be 2 UI—
64 UI depending on state. The digital phase-locked
loop used for timing recovery has 8 UI delay.
SYSCK Reference Clock
The LIU requires an externally applied clock, SYSCK
pins 3 and 35, for the clock and data recovery function
and the jitter attenuation option. SYSCK must be a con-
tinuously active (i.e., ungapped, unjittered, and
unswitched) and an independent reference clock such
as from an external system oscillator or system clock
for proper operation. It must not be derived from any
recovered line clock (i.e., from RLCK or any synthe-
sized frequency of RLCK).
SYSCK may be supplied in one of two formats. The for-
mat is selected for each channel by CKSEL pins 48
and 133. For CKSEL = 1, a clock at 16x the primary
line data rate clock (24.704 MHz for DS1 and
32.768 MHz for CEPT) is applied to SYSCK. For
CKSEL = 0, a primary line data rate clock (1.544 MHz
for DS1 and 2.048 MHz for CEPT) is applied to
SYSCK.
The CKSEL pin has an internal pull-up resistor allowing
the pin to be left open, i.e., a no connect, in applica-
tions using a 16x reference clock and pulled down to
ground for applications using a primary line data rate
clock.
16x SYSCK Reference Clock
The specifications for SYSCK using a 16x reference
clock are defined in Table 12. The 16x reference clock
is selected when CKSEL = 1.
Table 12. SYSCK (16x, CKSEL = 1) Timing
Specifications
* When JABW0 = 1 and the jitter attenuator is used in the receive
data path, the tolerance on SYSCK should be tightened to ±20 ppm
in order to meet the jitter accommodation requirements of TBR12/
13 as given in G.823 for line data rates of ±50 ppm.
If SYSCK is used as the source for AIS (see LIU Transmitter Alarm
Indication Signal Generator (XLAIS)), it must meet the nominal
transmission specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or
2.048 MHz ± 50 ppm for CEPT (E1).
Primary Line Rate SYSCK Reference Clock and
Internal Reference Clock Synthesizer
In some applications, it is more desirable to provide a
reference clock at the primary data rate. In such cases,
the LIU can utilize an internal 16x clock synthesizer
allowing the SYSCK pin to accept a primary data rate
clock. The specifications for SYSCK using a primary
rate reference clock are defined in Table 13.
Table 13. SYSCK (1x, CKSEL = 0) Timing
Specifications
* When JABW0 = 1 and the jitter attenuator is used in the receive
data path, the tolerance on SYSCK should be tightened to ±20 ppm
in order to meet the jitter accommodation requirements of TBR12/
13 as given in G.823 for line data rates of ±50 ppm.
If SYSCK is used as the source for AIS (see LIU Transmitter Alarm
Indication Signal Generator (XLAIS)), it must meet the nominal
transmission specifications of 1.544 MHz ± 32 ppm for DS1 (T1), or
2.048 MHz ± 50 ppm for CEPT (E1).
Parameter
Value
Unit
Min
Typ
Max
Frequency
DS1
CEPT
Range*,
Duty Cycle
—
—
24.704
32.768
—
—
—
—
100
60
MHz
MHz
ppm
%
–100
40
Parameter
Value
Unit
Min
Typ
Max
Frequency
DS1
CEPT
Range*,
Duty Cycle
Rise and Fall Times
(10%—90%)
—
—
1.544
2.048
—
—
—
—
—
100
60
5
MHz
MHz
ppm
%
ns
–100
40
—
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