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| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 65/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
65
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats
(continued)
The CRC-4 word, located in submultiframe N, is the
remainder after multiplication by x
4
and then division
(modulo 2) by the generator polynomial x
4
+ x + 1, of
the polynomial representation of the submultiframe N –
1. Representing the contents of the submultiframe
check block as a polynomial, the first bit in the block,
i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the
most significant bit and the least significant bit in the
check block is frame 7 or frame 15, bit 256. Similarly,
C
1
is defined to be the most significant bit of the
remainder and C
4
the least significant bit of the remain-
der. The encoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.2, follows:
I
The CRC-4 bits in the SMF are replaced by binary
zeros.
I
The SMF is then acted upon the multiplication/divi-
sion process referred to above.
I
The remainder resulting from the multiplication/divi-
sion process is stored, ready for insertion into the
respective CRC-4 locations of the next SMF.
The decoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.3, follows:
I
A received SMF is acted upon by the multiplication/
division process referred to above, after having its
CRC-4 bits extracted and replaced by zeros.
I
The remainder resulting from this division process is
then stored and subsequently compared on a bit-by-
bit basis with the CRC bits received in the next SMF.
I
If the remainder calculated in the decoder exactly
corresponds to the CRC-4 bits received in the next
SMF, it is assumed that the checked SMF is error-
free.
CEPT Loss of CRC-4 Multiframe Alignment
(LTS0MFA)
Loss of basic frame alignment forces the receive framer
into a loss of CRC-4 multiframe alignment state. This
state is reported by way of the status registers
FRM_SR1 bit 2. Once basic frame alignment is
achieved, a new search for CRC-4 multiframe align-
ment is initiated. During a loss of CRC-4 multiframe
alignment state:
I
The CRC-4 error counter is halted.
I
The CRC-4 error monitoring circuit for errored sec-
onds and severely errored seconds is halted.
I
The received E-bit counter is halted.
I
The received E-bit monitoring circuit for errored sec-
onds and severely errored seconds at the remote
end interface is halted.
I
Receive continuous E-bit monitoring is halted.
I
All receive Sa6 code monitoring and counting func-
tions are halted.
I
The updating of the receive Sa stack is halted and
the receive Sa stack interrupt is deactivated.
I
Optionally, A = 1 may be automatically transmitted to
the line if register FRM_PR27 bit 2 is set to 1.
I
Optionally, E = 0 may be automatically transmitted to
the line if register FRM_PR28 bit 4 is set to 1.
I
Optionally, if LTS0MFA monitoring in the perfor-
mance counters is enabled, by setting registers
FRM_PR14 through FRM_PR17 bit 1 to 1, then
these counts are incremented once per second for
the duration of the LTS0MFA state.
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