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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 33/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
33
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Transmit
(continued)
LIU Transmitter Configuration Modes
LIU Transmitter Zero Substitution Encoding
(CODE)
LIU transmitter zero substitution (B8ZS/HDB3) encod-
ing can be activated only in the single-rail (DUAL = 0)
system/framer interface mode. It is activated by setting
CODE = 1 (register LIU_REG3, bit 2). Data transmitted
from the framer interface on TPD-LIU will be B8ZS/
HDB3 encoded before appearing on TTIP and TRING
at the line interface.
LIU Transmitter Alarm Indication Signal Generator
(XLAIS)
When the transmit alarm indication signal control is set
(XLAIS = 1) for a given channel (see register
LIU_REG5, bit 1), a continuous stream of bipolar ones
is transmitted to the line interface. The internal LIU to
framer TPD interface (TPD) and internal LIU to framer
TND interface (TND) signals are ignored during this
mode. The XLAIS control is ignored when a remote
loopback (RLOOP) is selected using loopback control
bits LOOPA and LOOPB (register LIU_REG5, bits 2 to
3). The clock source used for the alarm indication sig-
nal is TLCK if present or INTSYSCK if TLCK is not
present. The clock tolerance must meet the nominal
transmission specifications of 1.544 MHz ± 32 ppm for
DS1 (T1) or 2.048 MHz ± 50 ppm CEPT (E1).
The XLAIS bit is defaulted to 1 on hardware reset
allowing the transmitter to send AIS as soon as clocks
are available, without needing to write the LIU regis-
ters
*
. Because the transmit equalization bits are
needed to determine the correct system rate (DS1/E1),
the reset default state of the equalization bits EQ2,
EQ1, EQ0 (register LIU_REG6, bits 0—2) can be pre-
determined by setting the DS1_CEPT pin (see
Table 7). The default transmit equalization is EQ2,
EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT
= 1, and EQ2, EQ1, and EQ0 = 110 (CEPT 120
/75
) when DS1_CEPT = 0. The transmit equalization bits
can be subsequently programmed to any state by writ-
ing the LIU register regardless of the state of the
DS1_CEPT pin. The DS1_CEPT pin is only used to
determine the reset default state of the equalization
bits.
LIU Transmitter Alarms
Loss of LIU Transmit Clock (LOTC) Alarm
A loss of LIU transmit clock alarm (LOTC = 1, see reg-
ister LIU_REG0, bit 3) is indicated if any of the clocks
used in the LIU transmitter paths are absent. This
includes loss of TLCK-LIU input, loss of RLCK-LIU dur-
ing remote loopback, loss of jitter attenuator output
clock (when enabled in transmit path), or the internal
loss of clock from the pulse-width controller. For all of
these conditions, the LIU transmitter timing clock is lost
and no data can be driven onto the line. Output drivers
TTIP and TRING are placed in a high-impedance state
when this alarm is active. The LOTC alarm asserts
between 3
μ
s and 16
μ
s after the clock is lost and
deasserts immediately after detecting the first clock
edge. The LOTC alarm status bit will latch the alarm
and remain set until being cleared by a read (clear on
read). Upon the transition from LOTC = 0 to LOTC = 1,
an interrupt will be generated if the LOTC interrupt
enable bit LOTCIE (register LIU_REG1, bit 3) is set.
The reset default is LOTCIE = 0.
An LOTC alarm may occur when RLOOP is activated
and deactivated due to the phase transient that occurs
as TLCK-LIU switches its source to and from RLCK-
LIU. Setting the RLOOP alarm prevention PRLALM = 1
(register LIU_REG4, bit 3) prevents the LOTC alarm
from occurring at the activation and deactivation of
RLOOP but allows the alarm to operate normally dur-
ing the RLOOP active period. The reset default is
PRLALM = 0.
LIU Transmitter Driver Monitor (TDM) Alarm
The transmit driver monitor detects two conditions: a
nonfunctional link due to faults on the primary of the
transmit line transformer and periods of no data trans-
mission. The TDM alarm (register LIU_REG0, bit 2) is
the OR’d function of both faults and provides informa-
tion about the integrity of the LIU transmitter signal
path.
* If TLCK from the framer is present, automatic transmission of AIS
upon reset will occur only if the CHI common control register
FRM_PR45 bit 0 = 0, the default, or low-frequency PLLCK mode. In
this case, PLLCK will be equal to the line transmit rate, either
1.544 MHz for DS1 or 2.048 MHz for CEPT.
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