Lucent Technologies Inc.
Lucent Technologies Inc.
171
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture
(continued)
Framer FDL Control Command Register (FRM_PR21)
The default value of this register is 00 (hex).
Table 147. Framer FDL Control Command Register (FRM_PR21) (675; C75)
Framer Transmit Line Idle Code Register (FRM_PR22)
The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex).
Table 148. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)
Framer System Stuffed Time-Slot Code Register (FRM_PR23)
The value programmed in this register is transmitted in the stuffed time slots on the CHI in the DS1 modes. The
default value is 7F (hex).
Table 149. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77)
Bit
0
1
2
3
4
5
Symbol
—
—
—
—
TFDLLAIS
TFDLSAIS
Description
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Transmit Facility Data Link AIS to the Line.
A 1 sends AIS in the line side data link.
Transmit Facility Data Link AIS to the System.
A 1 sends AIS in the system data link
side.
Transmit FDL Control Bit.
A 0 enables the transmission of the FDL bit from the internal
FDL-HDLC unit (default). A 1 enables the transmission of the FDL bit from either TFDL
input (pin 67 and 115) or from the internal transmit stack depending on the state of
FRM_PR29 bit 5—bit 7. When the SLC-96 stack transmission is enabled (register
FRM_PR26 bit 5—bit 7 = x10 (binary), the FDL bit is sourced from the SLC-96 transmit
stack (register FRM_PR31—FRM_PR35). Otherwise, it is sourced from TFDL
(pins 67/115).
Transmit ESF_PRM C/R = 1 (TC/R = 1).
A 0 transmits the ESF performance report mes-
sage with the C/R bit = 0. (See ANSIT1.403-1995 for the PRM structure and content.) A
1 transmits the ESF performance report message with the C/R bit = 1.
6
TFDLC
7
TC/R = 1
Bit
0—7
Symbol
TLIC0—TLIC7
Description
Transmit Line Idle Code 0—7.
These 8 bits define the idle code transmitted to the
line.
Bit
0—7
Symbol
SSTSC0—
SSTSC7
Description
System Stuffed Time-Slot Code 0—7.
These 8 bits define the idle code transmitted
in the stuffed time slots to the system (CHI).