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參數(shù)資料
| 型號： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁數(shù)： | 63/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
63
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats
(continued)
CEPT Loss of Basic Frame Alignment (LFA)
Frame alignment is assumed to be lost when:
I
As described in ITU Rec. G.706 Section 4.1.1, three
consecutive incorrect frame alignment signals have
been received.
I
So as to limit the effect of spurious frame alignment
signals, when bit 2 in time slot 0 in NOT FAS frames
have been received with an error on three consecu-
tive occasions.
I
Optionally, as described in ITU Rec. G.706 Section
4.3.2, by exceeding a count of >914 errored CRC-4
blocks out of 1000, with the understanding that a
count of
≥
915 errored CRC blocks indicates false
frame alignment.
I
On demand via the control registers.
In the LFA state:
I
No additional FAS or NOT FAS errors are processed.
I
The received remote frame alarm (received A bit) is
deactivated.
I
All NOT-FAS bit (Si bit, A bit, and Sa4 to Sa8 bits)
processing is halted.
I
Receive Sa6 status bits are set to 0.
I
Receive Sa6 code monitoring and counting is halted.
I
All receive Sa stack data updates are halted. The
receive Sa stack ready, register FRM_SR4 bit 6 and
bit 7, is set to 0. If enabled, the receive Sa stack
interrupt bit is set to 0.
I
Receive data link (RFDL) is set to 1 and RFDCLK
maintains previous alignment.
I
Optionally, the remote alarm indication (A = 1) may
be automatically transmitted to the line if register
FRM_PR27 bit 0 is set to 1.
I
Optionally, the alarm indication signal (AIS) may be
automatically transmitted to the system if register
FRM_PR19 bit 0 is set to 1.
I
If CRC-4 is enabled, loss of CRC-4 multiframe align-
ment is forced.
I
If CRC-4 is enabled, the monitoring and processing
of CRC-4 checksum errors is halted.
I
If CRC-4 is enabled, all monitoring and processing of
received E-bit information is halted.
I
If CRC-4 is enabled, the receive continuous E-bit
alarm is deactivated.
I
If CRC-4 is enabled, optionally, E bit = 0 is transmit-
ted to the line for the duration of loss of CRC-4 multi-
frame alignment if register FRM_PR28 bit 4 is set to
1.
I
If time slot 16 signaling is enabled, loss of the signal-
ing multiframe alignment is forced.
I
If time slot 16 signaling is enabled, updating of the
signaling data is halted.
CEPT Loss of Frame Alignment Recovery
Algorithm
The receive framer begins the search for basic frame
alignment one bit position beyond the position where
the LFA state was detected. As defined in ITU Rec.
G.706.4.1.2, frame alignment will be assumed to have
been recovered when the following sequence is
detected:
I
For the first time, the presence of the correct frame
alignment signal in frame n
I
The absence of the frame alignment signal in the fol-
lowing frame detected by verifying that bit 2 of the
basic frame is a 1 in frame n+ 1.
I
For the second time, the presence of the correct
frame alignment in the next frame, n+ 2.
Failure to meet the second or third bullet above will ini-
tiate a new basic frame search in frame n+ 2.
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