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| 型號(hào)： | T7630 |
| 英文描述： | T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) |
| 中文描述： | T7630雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ） |
| 文件頁(yè)數(shù)： | 174/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
174
L Lucent Technologies Inc.
Framer Register Architecture
(continued)
Framer Reset and Transparent Mode Control Register (FRM_PR26)
The default value of this register is 00 (hex).
Table 154. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A)
Bits
0
Symbol
SWRESET
Description
Framer Software Reset.
The framer and FDL sections are placed in the reset state for
four clock cycles of the frame internal line clock (RFRMCK). The parameter registers are
forced to the default values. This bit is self-cleared.
SWRESTART
Framer Software Restart.
The framer and FDL sections are placed in the reset state as
long as this bit is set to 1. The framer’s parameter registers are
not
changed from their
programmed state. The FDL parameter registers are changed from their programmed
state. This bit must be cleared.
FRFRM
Framer Reframe.
A 0-to-1 transition of this bit forces the receive framer into the loss of
frame alignment (LFA) state which forces a search of frame alignment. Subsequent
reframe commands must have this bit in the 0 state first.
TFM1
Transparent Framing Mode 1.
A 1 forces the transmit framer to pass system data
unmodified to the line and the receive framer to pass line data unmodified to the system.
The receive framer is forced
not
to align to the input receive data.
1
2
3
DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in time slot
0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this
bit in the F-bit position of the transmit line data. The receive framer inserts the bit in the
F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA.
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. Receive
line time slot 0 is inserted into time slot 0 of TCHIDATA.
Transparent Framing Mode 2.
A 1 forces the transmit framer to pass system data
unmodified to the line. The receive framer functions normally as programmed.
4
TFM2
DS1: register FRM_PR43 bit 2—bit 0 must be set to 000. The F bit is located in
time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and
places this bit in the F-bit position of the transmit line data.
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data.
System Frame Sync Mask.
A 1 masks the system frame synchronization signal in the
transmit framer section.
5
SYSFSM
Note
: The transmit framer must see at least one valid system synchronization pulse to
initialize its counts; afterwards, this bit may be set. For those applications that have jitter
on the transmit clock signal relative to the system clock signal, enable this bit so that the
jitter is isolated from the transmit framer.
Reserved.
Write to 0.
6—7
—
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| T7630 | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
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| T8100 | H.100/H.110 Interface and Time-Slot Interchanger |
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