參數(shù)資料
型號(hào): T7630
英文描述: T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
中文描述: T7630雙T1/E1的5.0V的短途終結(jié)者(終結(jié)者-Ⅱ)
文件頁(yè)數(shù): 120/210頁(yè)
文件大小: 3075K
代理商: T7630
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
120
L Lucent Technologies Inc.
JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:
I
Testing the connections between ICs on a particular board.
I
Observation of signals to the IC pins during normal operating functions.
I
Controlling the built-in self-test (BIST) of an IC. T7630 does not support BS-BIST.
Designed according to the IEEE* Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the
test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin
ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller,
an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and DCODE
register). The main component is the BS register that links all the chip pins to a shift register by means of special
logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the
T7630 (the mode multiplexer of the BS output cells may be shared). Figure 57 illustrates the block diagram of the
T7630’s BS test logic.
5-3923(F)r.4
Figure 57. Block Diagram of the T7630's Boundary-Scan Test Logic
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
BOUNDARY-SCAN REGISTER
TDI
TRST
TMS
TCK
TAP
CONTROLLER
INSTRUCTION
DECODER
OUT
TDO
IN
MUX
CHIP KERNEL
(UNAFFECTED BY BOUNDARY-SCAN TEST)
IDCODE REGISTER
BYPASS REGISTER
INSTRUCTION REGISTER
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