Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
99
Chapter 11
Mailbox Registers
Occasionally it is necessary to pass small amounts of data or commands between the PCI
bus and the Local bus. For example, an intelligent EPC based PCI disk controller may need
to receive
“
get sector
”
commands from the x86 system host. Such commands could be sent
to the local CPU by PCI-to-Local memory transfers into a command buffer, followed by a
PCI interrupt request to indicate transfer completion. Using this method, however, is very
inefficient, especially when only a handful of bytes need to be transferred.
To solve this problem, the EPC provides 16 mailbox registers which may be used to transmit
and receive small amounts of data between the local CPU and the PCI bus. In addition,
each mailbox register can request an interrupt to signal the receipt, or the demand, for more
data.
Mailbox registers are also commonly used to emulate hardware registers in systems
requiring backward register compatibility.
11.1
OVERVIEW
The EPC provides 16 8-bit mailbox registers arranged as contiguous bytes in both the Local
and PCI internal register apertures. Each mailbox register is a dual ported memory, capable
of generating an interrupt request whenever it is read or written from either side. Figure 52
shows a block diagram of the mailbox registers.
11.1.1
Accessing the Mailbox Registers
The mailbox registers are accessed from the Local bus through the Local-to-Internal
Register (LB_IO_BASE) aperture. Typically, LB_IO_BASE is programmed during system
initialization (see
“
Initialization
”
).
The mailbox registers are accessed from the PCI bus through the PCI-to-Internal Register
(PCI_IO_BASE) aperture. Alternatively, the mailbox registers can be accessed through PCI
configuration space for the EPC.
The mailbox registers may be accessed as byte, short, word, or multiple word quantities.