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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 93/190頁(yè) |
| 文件大小： | 1105K |
| 代理商： | V363EPC-50 |
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Local Bus Interface
BTERM Operation (961 and 962 mode Only)
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
83
-- identify the troublesome cycle by EPC
fix_qads <= (not l_ads_n) and pci_hlda and l_wr_n;
end process;
-- disconnect (block) the troublesome cycle from EPC
l_bterm_n = '0' when( not((l_be_n3 & l_be_n(1 downto 0))
= "000") and fix_qads='1') else
'1' when(pci_hlda = '1') else 'Z';
---------------------------
---------------------------
Bursts by the EPC are always terminated at a burst modulo page boundary. For example: if
a 1K burst length is selected then the EPC will never cross a 1K page boundary (it will never
burst from address XXXXX3FCH to XXXXX400H). Similarly, if a 16 byte (4 word) burst is
selected it will never burst from XXXXXX0CH to XXXXXX10H. This makes the EPC
comparable to processors and page mode memory devices.
8.4
BTERM OPERATION (961 AND 962 MODE ONLY)
This section is applicable only to the EPC
in 961 and 962 modes.
The BTERM signal is used in two ways. When the EPC is a local bus master, the BTERM
input acts as a "Burst Termination" input with the same timing as the READY input. When
the EPC is a local bus slave for local aperture to PCI read/write operations, the BTERM
signal can be programmed to drive as an output for time-out conditions.
Note that BTERM must have a pull up resistor on the pin even if it is not being used in as an
input or output as described below.
8.4.1
BTERM as an Input
The EPC will respond to BTERM together with READY as if BLAST had been asserted also
with READY. This will cause the ADS signal to be re-driven to start a new cycle where the
original burst left off. The sequence is depicted below: It begins as a normal EPC local bus
master cycle with HOLD/HLDA/ADS being driven in sequence. At LCLK 6 the first data is
READY and the cycle looks like a normal burst. However, at LCLK 7 BTERM is asserted
with READY and the cycle terminates as if BLAST had been asserted at that time. At LCLK
7 the EPC begins to drive ADS again and with the address for data item 3 left over from the
previous unfinished burst. This burst cycle terminates normally with BLAST and READY at
LCLK 12.
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