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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 49/190頁(yè) |
| 文件大小： | 1105K |
| 代理商： | V363EPC-50 |
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DMA Controller
DMA Transfers
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
41
6.1.6
DMA Transfer Size
The DMA controller performs all transfers in word (32 bits) sizes.
For the V350EPC where the local bus is 16-bit wide, a 16 to 32-bit conversion will occur (the
EPC will wait for a second 16-bit word before writing a 32-bit word to a PCI bus). DMA
transfers begin and end on a 32-bit boundary and local bus transfers will be done 16 bits at
a time (one data phase on the PCI bus will produce two data phases on the local bus). Byte
and short (16-bit) boundaries are not supported. There is no performance penalty for this
restriction. From a software standpoint, a programmer wishing to transfer byte data need
only normalize the byte pointers to the next inclusive word boundary. This will result in
transferring more bytedata than necessary, however, since the PCI bus transfers data in 32-
bit words, there is no negative performance effect.
6.1.6.1
Block Size
The largest block size that can be transferred in any single link is 4MB (minus 4 bytes). The
DMA address generator provides a 25 bit count. Therefore, if a DMA transfer crosses a
32MB boundary then the address will wrap to the bottom of the same 32MB boundary
instead of the next 32MB boundary. Larger block sizes or crosing of a 32MB boundary can
easily be accomplished using the chaining feature of the DMA controller.
6.1.7
Relationship to the Data Transfer Apertures
The DMA Controller does not use the data transfer apertures. The write FIFOs, however, are
shared between transfers initiated by a bus master through either the PCI-to-Local or Local-
to-PCI apertures, and by the DMA Controller. Figure 11 shows the usage of the write FIFOs
by both the DMA Controller and the data transfer apertures.
The read ahead FIFOs are onlyused during bus master read accesses through the data
transfer apertures; they are not used during DMA operations at all.
6.1.8
Automatic DMA Throttling
The DMA Controller has a built in throttling mechanism to prevent it from monopolizing the
write FIFO or target buses. The DMA Controller will not initiate a transfer if the target write
FIFO is more than half full. Once the write FIFO is drained below one quarter full, DMA
transfers involving the corresponding write FIFO will proceed.
6.1.9
Demand Mode DMA
Explicit hardware DMA request inputs can be used to throttle DMA transfers. This is
provided by the DREQ_EN bits in the DMA_LENGTHx registers which use INTC and/or
INTD as active low DMA request inputs. Hardware throttling works by allowing the source
data of a DMA transfer to be loaded only when the external DREQx pin is asserted. The act
of reading or writing local memory can be used as the DMA acknowledge.
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