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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 166/190頁(yè) |
| 文件大小： | 1105K |
| 代理商： | V363EPC-50 |
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Register Descriptions
Register Map
156
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
LB_ISTAT: LOCAL BUS INTERRUPT CONTROL AND STATUS REGISTER
Mnemonic:
Offset:
Size:
LB_ISTAT
76H
8 bits
LB_ISTAT
Bits
Mnemonic
Type
Reset
Value
Description
7
MAILBOX
a
a. This bit is a logical OR of all of the mailbox interrupt requests. It is only cleared when all of the
individual mailbox interrupt requests have been cleared via reading or writing the applicable mailbox
register. See the "Mailbox Register" section of the "Bridge Operation" chapter for more information.
b. Note: All writable status bits are cleared by writing
’
0
’
. Writing
’
1
’
has no effect.
R
0H
1 = an interrupt has been requested by one or more of the
mailbox registers
0 = no mailbox interrupts pending
1 = Master Abort or lack of Device Select has been seen during a
local bus to PCI bus read access and an interrupt request for
such events has been enabled; clear by writing "0"
0 = no local bus read of PCI space error interrupt request is
pending.
1 = Master Abort or lack of Device Select is seen during a local
bus to PCI bus write access and an interrupt request for such
events has been enabled; clear by writing "0"
0 = no local bus write to PCI space error interrupt request is
pending.
1 = a PCI interrupt pin has requested an interrupt
0 = no pending PCI interrupt events
PCI Parity Error Interrupt: This bit is set in response to parity error
seen on the PCI bus as a result of the VxxxEPC acting as either a
master or a slave for the cycle.
I2O Inbound Post Queue Write Interrupt: This bit is set when 3
conditions are met: I2O is enabled, the corresponding bit in
LB_IMASK is enabled and the inbound post list is written.
Cleared by writing
‘
0
’
.
1 = DMA channel 1 has requested an interrupt;clear by writing"0"
0 = DMA channel 1 has not requested an interrupt.
1 = DMA channel 0 has requested an interrupt;clear by writing "0"
0 = DMA channel 0 has not requested an interrupt.
6
PCI_RD
FRW
0H
5
PCI_WR
FRW
0H
4
PCI_INT
b
FRW
0H
3
PCI_PERR
RW
0H
2
I2O_QWR
a
RW
0H
1
DMA1
FRW
0H
0
DMA0
FRW
0H
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