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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 46/190頁(yè) |
| 文件大?。?/td> | 1105K |
| 代理商： | V363EPC-50 |
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DMA Controller
DMA Transfers
38
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
cycle can be programmed via the
DMA_WTYPE
bits (
DMA Write to PCI Bus Command Type
) in
the PCI_CFG register. It defaults to a value of 3h which produces a memory write command
of "0111".
After each local bus read transfer has completed, the local address is incremented and the
transfer count register is decremented. The DMA controller will continue to repeat the above
process until the transfer count reaches zero. Since transfer count is tracked on the source
readcycle (as opposed to the destination writecycle), polling the transfer count register for a
zero value is NOT a reliable way to ensure that the transfer is complete since the data may
not yet be written to the destination and may be sitting in the FIFO. To determine that a DMA
transfer is finished and it is safe to reprogram it, the DMA_IPR bit in the DMA_CSRx register
should be polled for
’
0
’
. If DMA_IPR is not clear, the contents of the destination address
should not be changed.
When the transfer count has reached zero, and the destination data has been written
completely, the DMA controller will either generate a
“
process complete
”
interrupt, or fetch
the next block transfer descriptor (if programmed for chaining). Block chaining is described
below.
6.1.2
PCI Bus to Local Bus DMA Transfers
PCI to Local bus DMA transfers operate nearly identically to the Local to PCI DMA transfers
described above. In this case, the data is read from the PCI side of the bridge (using a PCI
“
Read Memory
”
command) and then posted in the PCI-to-Local write FIFO.
A flowchart of basic DMA operation is shown in Figure 10.
6.1.2.1
Applications)
A Special Note on Byte Enables (Using DMA in FIFO
When using the DMA to transfer from PCI to a FIFO on the local bus there is a special
consideration that must be accounted for. If a PCI burst read of source data is disconnected
without data
1
by the slave device then a
“
dummy
”
data will be written to the local bus. This
“
dummy
”
data is identified by the byte enables being all de-asserted. This does not cause a
problem for memory systems that implement a write-per-byte (as most do). However, an
application involving a FIFO must cause the cycle to be ignored (i.e. don't push) when
BE#[3:0] =
“
1111
”
.
6.1.3
DMA Block Chaining
Upon completion of a single block transfer, the DMA Controller can be programmed to
automatically fetch a new control block descriptor with the parameters for a subsequent
block. The descriptor includes the values for the PCI start address, Local start address,
transfer length, next control block descriptor address and control information. The initial
1. Disconnecting without data is inefficient and should be avoided by slave devices. For this reason the
EPC (as a slave device) does a disconect WITH data when necessary.
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