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參數(shù)資料
| 型號： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 18/190頁 |
| 文件大小： | 1105K |
| 代理商： | V363EPC-50 |
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Bridge Operation Overview
Operational Example
10
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
delivered from PCI space.
For example, let
’
s look at the case where the local master wants to read from a register on
an add-in card located at A000.0010H in PCI space. Let
’
s assume the EPC is programmed
to translate accesses to Local-to-PCI aperture 0 from E00n.nnnn in local memory to
A00n.nnnnH in PCI space. To read from A000.0010H, the local master initiates a read to
E000.0010H. The EPC sees this read, recognizes it as being within Local-to-PCI aperture 0
and "captures" it for bridging to the PCI bus. Since the data is not immediately available to
return to the host, the bridge returns a NOT READY indication to the local processor.
Simultaneously, the EPC requests the PCI bus. Once granted the bus, the EPC begins to
read from the translated address (A000.0010H) and transfers that data back across the
bridge to the local processor. As each datum becomes available on the local side, READY is
returned to complete the local bus request. Just as in the write transfer case, the EPC can
be programmed to perform byte order conversion as the data flows through the bridge. In
order to improve system bandwidth, the EPC can be programmed to prefetch data from the
PCI bus. The prefetched data will be
‘
cached
’
in the bridge until the next access.
2.1.3
PCI Write to Local Space
PCI bus masters gain access to the local memory space through the PCI-to-Local bus
apertures. In our example, the PCI-to-Local aperture has been programmed to respond to
PCI accesses within the 1000.0000H to 100F.FFFFH range (a 1 megabyte window). For a
PCI master to write into the EPC
’
s local memory, it simply writes to a PCI location falling
within a PCI-to-Local aperture window.
For example, let
’
s assume the PCI master wants to write to location 2000.0030H in the
EPC
’
s local memory space. Since the bridge is programmed to respond to accesses in the
1000.0000H to 100F.FFFFH range we will need to re-map the address so that the proper
translation occurs. The PCI master now writes data to PCI location 1000.0030H, that access
is captured by the bridge and buffered within the PCI-to-Local write FIFO. The PCI master
completes the write and relinquishes the bus. Simultaneously, the address of the access is
translated within the bridge, and the EPC requests access to the local bus (the protocol
used to gain local bus mastership is processor version dependent). Once granted the local
bus, the EPC will write the captured data in the new location in local memory space
(2000.0030H). Data byte order translation is also available in the PCI-to-Local direction.
2.1.4
PCI Reads from Local Space
As you might expect, PCI reads from local space closely mirror local reads from PCI space.
Let
’
s assume the same conditions as the previous example, except in this case the PCI
master wants to read from location 2000.0030H in local memory space. In this case, the PCI
master reads from location 1000.0030H in PCI space (remember address translation will do
this automatically once configured). The bridge immediately responds by deasserting "target
ready" (TRDY) to inform the PCI master that it will need to wait for the data to be fetched
from the local side. Simultaneously, the EPC requests the local bus. Once granted the local
bus, the EPC will read from location 2000.0030H and forward that data across the bridge to
the PCI side. When the data is valid on the PCI side, TRDY will be asserted to signal
completion of the read. As with the Local-to-PCI transfer, the EPC can prefetch data and
cache it.
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