Register Descriptions
Register Map
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
171
QBA_MAP : LOCATING THE QUEUE IN LOCAL MEMORY
a
Mnemonic:
Offset:
Size:
QBA_MAP
DCH
32 bits
I2O MESSAGE UNIT POINTERS
Offset:
Size:
A0H-BFH
32 bits each
QBA_MAP
Bits
Mnemonic
Type
Reset
Value
Description
31-20
BASE
RW
0H
Queue Base Address: These bits are used to generate bits 31-20
of all Inbound/Outbound pointers.egister bits so that lower bits of
the decode are masked off.
reserved
19-10
-
R
0H
10-8
QSIZE
RW
0H
Queue Size: The size of the aperture is determined as follows::
7-1
-
R
0H
reserved
I2O Device On Line: when clear (0), the VxxxEPC will return
0xFFFFFFFF when the inbound and outbound ports are read.
This bit should only be enabled after the queues have been
initialized by the local processor and it is ready to accept an
inbound MFA. This bit must be clear in order for the local
processor to modify the contents of the OFL_HEAD, OPL_TAIL,
IPL_HEAD and IFL_TAIL registers.
0
ONLINE
RW
0H
Reg. Name
Offset
Description
Pointer Maintenance
OFL_HEAD
0xBC
Outbound Free List Head Pointer
PCI write of Outbound Port auto-
increments
OFL_TAIL
0xB8
Outbound Free List Tail Pointer
Updated by local processor
OPL_HEAD
0xB4
Outbound Post List Head Pointer
Updated by local processor
OPL_TAIL
0xB0
Outbound Post List Tail Pointer
PCI read of Outbound Port auto-
increments
IPL_HEAD
0xAC
Inbound Post List Head Pointer
PCI write of Inbound Port auto-
increments
IPL_TAIL
0xA8
Inbound Post List Tail Pointer
Updated by local processor
IFL_HEAD
0xA4
Inbound Free List Head Pointer
Updated by local processor
IFL_TAIL
0xA0
Inbound Free List Tail Pointer
PCI read of Inbound Port auto-
increments
QSIZE
Size
Auto Increment
Mask
0x3FFC
0x7FFC
0xFFFC
0x1FFFC
0x3FFFC
000
001
010
011
100
others
4K entries (16K Bytes)
8K entries (32K Bytes)
16K entries (64K Bytes)
32K entries (128K Bytes)
64K entries (256K Bytes)
reserved