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參數(shù)資料
| 型號： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 52/190頁 |
| 文件大小： | 1105K |
| 代理商： | V363EPC-50 |
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DMA Controller
Programming the DMA Controller
44
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
The PCI memory starting address is programmed through the DMA_PCI_ADDR0 (or
DMA_PCI_ADDR1) register. The PCI memory address is word aligned. The EPC sets the 2
least significant bits of DMA_PCI_ADDRx to zero in order to force word alignment. The DMA
Controller can only generate PCI Read and PCI Write commands on the PCI bus.
Both address registers are automatically incremented after each word is transferred. These
registers may be read at any time to determine the current value of the pointers. The
address registers may also be written to at any time, however, the programmer should check
the
“
In Progress
”
bit (in the DMA_CSRx register) before modifying the pointers of a DMA
operation in progress. Failure to do so could result in undefined bridge operation.
As previously mentioned, the DMA Controller is unrelated to the data transfer registers. The
address translation, endian conversion, and prefetching options for the data transfer
apertures will not affect DMA operation, even if the DMA controller is performing a transfer
involving memory locations that fall within a data transfer aperture.
6.2.2
Setting the Transfer Count
The transfer count is stored in the DMA_LENGTHx register. The transfer count is in 32-bit
words. The maximum value for the transfer count is 1 megaword or 4 megabytes (longer
transfers may be performed using block chaining).
The transfer count is decremented after each word of data is transferred. The
DMA_LENGTHx registers may be read at any time to determine the current value transfer
count. The transfer count registers may also be written to at any time, however, the
programmer should check the
“
In Progress" bit (DMA_IPR bit in the DMA_CSRx register)
before modifying the transfer count for a DMA operation in progress. It is possible to halt
DMA operation immediately, by setting the transfer count of a DMA process in progress to
zero.
6.2.3
Setting the Transfer Direction
The DMA transfer direction - PCI-to-Local or Local-to-PCI - is set by the DIRECTION bit in
the DMA_CSRx register. This bit must not be changed while a DMA process is running (as
indicated by the state of the DMA_IPR bit for each channel.) Changing the DIRECTION bit
while a DMA process is running will result in undefined bridge operation.
6.2.4
Byte Order Conversion
Each DMA channel can convert data byte order on-the-fly. The SWAP bits in the
DMA_CSRx register control the three conversion options: 8-bit, 16-bit, and 32-bit. Byte order
conversion by the DMA Controller is identical to that performed by the data transfer
apertures.
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