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參數(shù)資料
| 型號： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 124/190頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | V363EPC-50 |
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Interrupt Control
PCI Interrupt Control Unit (PICU)
114
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
13.2.2
PCI Interrupt Pins (INTA through INTD)
The PCI Specification provides for four shared PCI interrupt request pins: INTA through
INTD. Typically, these interrupts are driven by the target devices in a system and received
by the host bridge device. Since the EPC can be used as either a host or target bridge, the
capability is provided to either receive interrupts or drive interrupt requests on the INTA
through INTD pins.
13.2.2.1
Configuring a PCI Interrupt Pin as an Interrupt Request
Output
Any of the INTx pins can be configured as an output pin. However, only oneof the INTx pins
can be designated as the destination for mailbox, local direct, and DMA interrupt requests
(chosen by the INT_PIN field in the PCI_BPARAM register). The remaining INTx outputs
can be programmed to reflect the state of other INTx pins configured as inputs(see
Crosspoint Routing Mechanism, below).
The direction of the INTx pins is set via the MODEx fields in the PCI Interrupt Configuration
register (PCI_INT_CFG). Pins configured as outputs are always active low and are software
cleared. Software cleared outputs will go inactive when the corresponding bit in the
PCI_INT_STAT register is cleared.
13.2.2.2
Configuring a PCI Interrupt Pin as an Interrupt Request
Input
Any of the INTx pins may be configured as inputs. The direction and detection mechanism
for INTx pins is controlled by the MODEx field in the PCI_INT_CFG register. INTx inputs
may be either edge or level sensitive. Edge sensitive pins will generate an interrupt event
when a high-to-low transition is seen on the pin. Level triggered inputs will generate an
interrupt event whenever the state of the INTx pin is low. (Note that level triggered inputs will
generate another interrupt event if a previous request is cleared AND the corresponding
INTx pin is still at a logic
“
0
”
.)
PCI interrupt inputs will post interrupt requests in the PCI_INT_STAT register only when they
are routed to a PCI interrupt outputthrough the crosspoint routing mechanism (see below).
13.2.2.3
Crosspoint Interrupt Routing Mechanism
Many embedded designs will require the ability to control multiple PCI interrupt input and
output events. The EPC
’
s crosspoint interrupt routing mechanism allows for extremely
flexible interrupt request routing between the four interrupt pins.
For example, consider the case of an expandable network router using PCI as the
backplane. In such a system there may be no single
“
host processor
”
. Each plug in board
may act as a host processor from time to time, and will need the ability to both receive
interrupt requests as well as post them. It would be nice if such a system could be designed
to be
“
plug and play
”
, so that when a new board was added, it automatically configured
some of its interrupts as inputs, and some as outputs dynamically The interrupt crosspoint
routing mechanism allows the system designer to do just that.
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