Register Descriptions
Register Map
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
137
PCI_BASE1: PCI TO LOCAL BUS APERTURE 1 BASE ADDRESS
1
Mnemonic:
Offset:
Size:
PCI_BASE1
18H
32 bits
PCI_SUB_VENDOR: PCI SUBSYSTEM VENDOR
Mnemonic:
Offset:
Size:
PCI_SUB_VENDOR
2CH
16 bits
1.Only available when I2O mode is disabled.
PCI_BASE1
Bits
Mnemonic
Type
Reset
Value
Description
31-20
ADR_BASE
FRW
0H
Base Address: If the value of ADR_BASE matches that of
AD[31:20] during the address phase of a PCI access then a
match is detected.
In legacy DOS mode the address comparison has increased
granularity (see DOS Compatibility chapter).
Base address bits used only for DOS compatibility mode. See PC
Compatibility chapter. These bits read back as
’
0
’
unless DOS
mode is selected in the PCI_MAP1 register.
reserved
DOS Mode Memory Size: When IO=0 and DOS mode is
selected, these bits set the size of the real mode DOS memory
hole:
100 = 16K bytes (A[31:14])
101 = 32K bytes (A[31:15])
110 = 64K bytes (A[31:16])
111 = 128K bytes (A[31:17])
others = disabled
These bits read back as
’
0
’
unless DOS mode is selected in the
PCI_MAP1 register.
reserved
Prefetchable:
1 = Enable read prefetching for this aperture
0 = Disable read prefetching for this aperture
When LOCK is disabled and both the IO and PREFETCH bits are
written to
’
1
’
, the PREFETCH bit will read
’
0
’
even though it is
internally set to
’
1
’
and the aperture will exhibit prefetch behavior.
Address Range Type: These read only bits are hardwired to "00"
to indicate that the device can be mapped anywhere in the 32 bit
address space.
1 = The PCI-to-Local aperture 0 is in PCI IO space
0 = The PCI-to-Local aperture 0 is in PCI memory space
19-14
ADR_BASEL
FRW
R
0H
13-11
-
R
0H
10-8
DOS_MEM
FRW
R
0H
7-4
-
R
0H
3
PREFETCH
FR
0H
2-1
TYPE
R
0H
0
IO
FR
0H
PCI_SUB_VENDOR
Reset
Value
Subsystem Vendor ID: firmware programmable (PCI 2.1 and
Windows95
required)
Bits
Mnemonic
Type
Description
15-0
VENDOR
FRW
0H