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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 126/190頁(yè) |
| 文件大?。?/td> | 1105K |
| 代理商： | V363EPC-50 |
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Interrupt Control
PCI Interrupt Control Unit (PICU)
116
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
Clearing the DMA interrupt requests is achieved by writing "1" to the corresponding bit in the
PCI_INT_STAT register. Note that clearing a DMA interrupt request in PCI_INT_STAT has
no affect on the DMA interrupt request bits in the LB_STAT register.
Mailbox interrupt requests are only cleared by clearing the individual mailbox interrupt
requests in the mailbox register unit.
13.2.3.2
Local Direct Interrupt Request
The Local processor may request a PCI interrupt by setting the LOCAL bit in the
PCI_INT_STAT register. The LOCAL bit can be cleared from the PCI or Local side of the
bridge.
13.2.3.3
Routing the Internal PCI Interrupt Requests to an INTx
Pin
Only one INTx pin can be the destination for internal PCI interrupts. The specific pin is
determined by programming the INT_PIN field in the PCI_BPARAM register. The pin used
for this purpose may also be used as the destination for crosspoint routed INTx interrupts.
13.2.4
PICU Configuration Example
An example may be helpful in describing the operation of the PCI Interrupt Control Unit.
Figure 59 shows a system block diagram for the following example. The interrupt pin usage
is detailed in Table 19.
First, we
’
ll need to mask DMA and mailbox interrupts from appearing on the INTC pin when
we
“
turn it on
”
as an output (this will prevent spurious interrupts from occurring). These
interrupts are disabled by clearing the MAILBOX and DMA0/1 bits in the PCI_INT_CFG
register.
The next step is to configure INTD and INTC as outputs. This is done by setting the
appropriate mode in the MODED and MODEC fields in the PCI_INT_CFG register. We
’
ll
choose
“
software cleared
”
for both (MODEx=10). Since INTC needs to be able to drive the
local direct interrupt onto the PCI bus, we must also set INT_PIN field in the PCI_BPARAM
register to
“
011
”
(this sets INTC as the
“
receiver
”
for internal PCI interrupts). Because all of
the PCI interrupts are open drain (by PCI definition), we
’
ll need to make sure the hardware
guys put a pullup resister on the INTD pin that
’
s used as a local interrupt (it
’
s not on the
block diagram).
Finally, we need to configure the INTA and INTB pins as inputs to INTD (the PCI interrupt
routing request pin). This is done by setting the INTA_TO_D and INTB_TO_D bits in the
PCI_INT_CFG register. Configuration is now complete.
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