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Register Descriptions
Register Map
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
157
LB_IMASK: LOCAL BUS INTERRUPT MASK REGISTER
Mnemonic:
Offset:
Size:
LB_IMASK
77H
8 bits
LB_IMASK
Bits
Mnemonic
Type
Reset
Value
Description
7
MAILBOX
FRW
0H
Global Mailbox Interrupt Enable:
1 = mailbox interrupts are enabled
0 = all mailbox interrupts are masked
PCI Read Error Interrupt Enable:
1 = enable local interrrupt requests for PCI read errors
0 = mask local interrrupt requests for PCI read errors
PCI Write Error Interrupt Enable:
1 = enable local interrrupt requests for PCI write errors
0 = mask local interrrupt requests for PCI write errors
Global PCI Interrupt to Local Interrupt Enable:
1 = enable PCI interrupt requests to request a local interrupt
0 = mask PCI interrupt requests to request a local interrupt
PCI Parity Error Interrupt Enable: When enabled (1) the
corresponding bit in LB_ISTAT is set in response to a parity error
event seen on the PCI bus. In order for a PCI parity event to be
detected one or more of the MASTER_PI and/or the SLAVE_PI
bits in PCI_INT_CFG must be enabled in addition to this bit.
I2O Inbound Post Queue Write Interrupt Enable: Set (1) to enable
inbound post queue write cycles to generate interrupts on the
Local Bus.
DMA Channel 1 Interrupt Enable:
1 = enable DMA Channel 1 interrupt requests
0 = mask DMA Channel 1 interrupt requests
DMA Channel 0 Interrupt Enable:
1 = enable DMA Channel 0 interrupt requests
0 = mask DMA Channel 0 interrupt requests
6
PCI_RD
FRW
0H
5
PCI_WR
FRW
0H
4
PCI_INT
FRW
0H
3
PCI_PERR
RW
0H
2
I2O_QWR
RW
0H
1
DMA1
FRW
0H
0
DMA0
FRW
0H