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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 164/190頁(yè) |
| 文件大?。?/td> | 1105K |
| 代理商： | V363EPC-50 |
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Register Descriptions
Register Map
154
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
FIFO_PRIORITY: FIFO PRIORITY CONTROL REGISTER
Mnemonic:
Offset:
Size:
FIFO_PRIORITY
72H
16 bit
FIFO_PRIORITY
Reset
Value
0H
reserved
Local Bus Request Priority: this controls the relative priority of
pending transfers involving PCI to local bus.
0 = PCI write to local bus has priority over PCI read from local
bus
1 = PCI read from local bus has priority over PCI write to local
bus
Local Bus Read Flush Strategy for Aperture 1: this controls the
condition that will cause Aperture 1 Local bus read prefetch FIFO
to be flushed for the purpose of maintaining data coherency:
00 = Local bus to PCI writes never cause a flush
a
01 = Flush at the end of a burst read (don
’
t keep extra data)
10 = Local bus to PCI write via aperture 1 will cause a flush (but
not aperture 0)
11 = Any local bus to PCI write will cause a flush
Local Bus Read Flush Strategy for Aperture 0: this controls the
condition that will cause aperture 0 Local bus read prefetch FIFO
to be flushed for the purpose of maintaining data coherency:
00 = Local bus to PCI writes never cause a flush
a
01 = Flush at the end of a burst read (don
’
t keep extra data)
10 = Local bus to PCI write via aperture 0 will cause a flush (but
not aperture 1)
11 = Any local bus to PCI write will cause a flush
0H
reserved
PCI Bus Request Priority: this controls the relative priority of
pending transfers involving local bus to PCI bus.
0 = Local bus write to PCI has priority over Local bus read from
PCI
1 = Local bus read from PCI has priority over Local bus write to
PCI
PCI Read Flush Strategy for Aperture 1: this controls the
condition that will cause Aperture 1 PCI read prefetch FIFO to be
flushed for the purpose of maintaining data coherency:
00 = PCI to local bus writes never cause a flush
a
01 = Flush at the end of a burst read (don
’
t keep extra data)
10 = PCI to local bus write via aperture 1 will cause a flush (but
not writes to aperture 0)
11 = Any PCI to local bus write will cause a flush
PCI Read Flush Strategy for Aperture 0: this controls the
condition that will cause aperture 0 PCI read prefetch FIFO to be
flushed for the purpose of maintaining data coherency:
00 = PCI to local bus writes never cause a flush
a
01 = Flush at the end of a burst read (don
’
t keep extra data)
10 = PCI to local bus write via aperture 0 will cause a flush (but
not writes to aperture 1)
11 = Any PCI to local bus write will cause a flush
Bits
Mnemonic
Type
Description
15-13
-
R
12
LOCAL
FRW
0H
11-10
LB_RD1
FRW
0H
a.Only this option should be chosen when prefetching is disabled for the aperture. When prefetching
is disabled, there is never any prefetch data to flush anyway.
9-8
LB_RD0
FRW
0H
7-5
-
R
4
PCI
FRW
0H
3-2
PCI_RD1
FRW
0H
1-0
PCI_RD0
FRW
0H
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