
Register Descriptions
Register Map
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
143
PCI_I2O_MAP: PCI BUS I
2
O ATU LOCAL BUS ADDRESS MAP
1
Mnemonic:
Offset:
Size:
PCI_I2O_MAP
44H
32 bits
1.Only available when I2O mode is enabled
PCI_I2O_MAP
Bits
Mnemonic
Type
Reset
Value
Description
31-20
MAP_ADR
FRW
0H
Map Address: These bits correspond to bits LAD(31:20) in local
address space when a PCI to Local access is made. Address bits
LAD(19:2) are derived from the PCI bus itself (for a 1MB aperture
size). If the size of the aperture is increased, then the lower bits of
MAP_ADR become masked off according to the ADR_SIZE bits
in the PCI_MAP registers.
reserved
Read Post Disable: When set '1' the very first read of a burst read
from the corresponding aperture will not generate a STOP#.
reserved
Byte Swap Control: Selects byte lane swapping for read and
write cycles according to the following table:
19-16
-
R
0H
15
RD_POST_DIS
FR
0H
14-10
-
R
0H
9-8
SWAP
FRW
0H
Auto Swap: When local bus BE[3:0] =
“
1100
”
or
“
0011
”
then a 16
bit swap is done. When local bus BE[3:0] =
“
1110
”
,
“
1101
”
,
“
1011
”
or
“
0111
”
then an 8 bit swap is done. Any other combination
results in non-swapped data.
Aperture Size: Legacy DOS mode uses a different decoding
scheme described in the "PC Compatibility" chapter of the
manual.
7-4
ADR_SIZE
FRW
0H
3-2
-
R
0H
reserved
SWAP
00
D[31:24]
Q[31:24]
D[23:26]
Q[23:16]
D[15:8]
Q[15:8]
D[7:0]
Q[7:0]
no swap, 32
bit
16 bit
8 bit
01
10
11
Q[15:8]
Q[7:0]
Q[7:0]
Q[15:8]
Q[31:24]
Q[23:16]
Q[23:16]
Q[31:24]
Auto Swap
ADDR_SIZE
0000
0001
0010
0011
0100
Size
1MB
2MB
4MB
8MB
Valid ADR BASE Bits
31:20
31:21
31:22
31:23
31:24 (mem)
31:8 (IO)
31:25 (mem)
31:9 (IO)
31:26 (mem)
31:10 (IO)
31:27 (mem)
31:11 (IO)
31:28
31:29
31:30
31:20
16MB memory
256 byte I/O
32MB memory
512 byte I/O
64MB memory
1024 byte I/O
128MB memory
2048 byte I/O
256MB
512MB
1GB
1MB DOS Mode
(PCI_MAP1 only)
-
0101
0110
0111
1000
1001
1010
11xx
others
reserved