FIFO Architecture and Operation
FIFO Data Coherency Options
Copyright 1997-2000, V3 Semiconductor Inc.
EPC User
’
s Manual Revision 1.05
35
5.5.2
Monitoring the Status of Read and Write FIFOs
The two write FIFOs and four read FIFOs each provide an indication of their relative
“
fullness
”
through bits in the FIFO_STATUS register. This information can be used to help
tune
“
filling
”
and
“
draining
”
strategies, as well as to determine when there is room available
in the FIFOs for additional transactions.
The status bits for the write FIFOs indicate both the fullness of the FIFOs as well as whether
the FIFOs are in the process of filling or draining. Two bits are used in the P2L_WR and
L2P_WR fields in the FIFO_STATUS register. A description of these bits is shown in
Figure 8.
Each write FIFO has a two bit flag that indicates whether there is room for additional data.
The read FIFO status bit encoding is shown in the Register Descriptions chapter.
Figure 8: Write FIFO Status Bits
5.5.3
Ensuring the Completion of a Posted Write
Occasionally, the system software will need to ensure that a posted write has completed on
the PCI bus. There are two methods available:
Software Polling.
Before issuing the write transfer, wait for the corresponding write
FIFO to become empty (by monitoring the FIFO status bits). Then post the write and
begin monitoring the status bits again. It is a good idea to check the PCI_STATUS
register to see if any errors occurred (e.g. a Master or Target Abort).
Hardware Stall
. Program the FIFO priority for writes-ahead-of-reads. First post the
write in the write FIFO, then attempt a dummy read from the same aperture. The
dummy read will lock the local bus until the write completes. (Note: systems using
V3 Semiconductor memory controllers must take into account the effect of the bus
watch timers if those features are enabled!).
0
1
2
62
63
64
00
01
11
10
01
01
11
11
Number of Words in the Write FIFO
Value in L2P_WR or P2L_WR Field