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參數(shù)資料
| 型號(hào)： | V363EPC-50 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 90/190頁(yè) |
| 文件大?。?/td> | 1105K |
| 代理商： | V363EPC-50 |
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Local Bus Interface
Master Mode
80
EPC User
’
s Manual Revision 1.05
Copyright 1997-2000, V3 Semiconductor Inc.
8.2.4
i960 Local Bus Reads and Writes
The local bus protocol used by the EPC family components is identical to that of the target
processor: V960EPC duplicates the i960Sx protocol, the V961EPC duplicates the i960Jx
protocol, and the V962EPC duplicates the i960Cx/Hx protocol.
All EPC
’
s support bursts longer in length than the i960 processor limit of 4 words (8
transaction on the i960Sx devices). The maximum burst length supported is 256 words. The
end of the burst is indicated by the BLAST signal, as is the case with "standard" i960 buses.
The burst length on the local bus is programmable via the LBRST_MAX field in the
FIFO_CFG register. Bursts may also be terminated at any time
1
by asserting the BTERM
signal. The burst will re-start with another ADS assertion at the point it was terminated.
V3 has chosen not to duplicate the wait-state control logic found in the i960Cx (MCON
registers) and i960Hx (PMCON registers).
2
8.2.5
Am29K Local Bus Reads and Writes
The V292EPC provides two different local bus protocols for Am29030/40 style busses: high-
performance mode and strict compatibility mode. The two modes differ in the BURST signal
assertion timing and in the length of bursts supported.
8.2.5.1
Strict Compatibility Mode
In strict compatibility mode the BURST signal is asserted coincident with the assertion of
LREQ (see Figure 39). This mode duplicates the bus protocol shown in the Am29030/40
documentation. When a series of access cycles are done by the V360EPC (292 mode) on
the local bus (such as a series of burst writes) the LREQ signal will be de-asserted for one
cycle between bursts. This is done so that the BURST and LREQ signals can occur
simultaneously at the beginning of a burst or non-burst cycle.
1. BTERM should only be asserted for 32 bit regions or only at a 32 bit boundary for an 8/16
bit region
2. This logic is of no use in systems using DRAM as main memory, as the wait-state profile
for DRAMs is indeterminate (due to refresh cycles.)
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| V375A12M300A2L | Analog IC |
| V375A12M300A3 | Analog IC |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| V363EPC-50LP | 制造商:Rochester Electronics LLC 功能描述: 制造商:QuickLogic Corporation 功能描述: |
| V363EPC-50LPN | 制造商:Rochester Electronics LLC 功能描述: 制造商:QuickLogic Corporation 功能描述: |
| V363ME01-LF | 制造商:ZCOMM 制造商全稱:ZCOMM 功能描述:Voltage-Controlled Oscillator Surface Mount Module |
| V363ME01-LF_10 | 制造商:ZCOMM 制造商全稱:ZCOMM 功能描述:Voltage-Controlled Oscillator Surface Mount Module |
| V364 | 制造商:VARTA 功能描述: |
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