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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 11/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
The first setting relates to the Auto-Negotiation
function. The IP100 PHY layer performs the
Auto-Negotiation process, and the host system
must communicate with the PHY to determine the
link status. Once the result of Auto-Negotiation is
determined, if a full duplex mode has been chosen,
the host system must set the FullDuplexEnable bit
in the MACCtrl0 register. Other modes chosen
during Auto-Negotiation do not require any IP100
register settings.
The ReceiveMode register determines which types
of frames, based on address matching mechanism,
the IP100 will receive. The end station address is
loaded from the EEPROM, or the host system can
set the address directly. Then, by setting the
ReceiveUnicast bit in the ReceiveMode register, the
IP100 will receive unicast frames whose destination
address matches the value in the StationAddress
register.
The ReceiveMulticastHash bit in ReceiveMode
enables a filtering mechanism for Ethernet multicast
frames. This filtering mechanism uses a 64-bit hash
table (HashTable register) for selective reception of
Ethernet multicast frames.
Additionally, Ethernet frames containing IP multicast
destination addresses can also be received by
setting
the
ReceiveIPMulticast
ReceiveMode register. IP multicast, or Host
Extension for IP Multicasting, datagrams map to
frames with Ethernet destination addresses of
0x01005e******
(where
hexadecimal value).
The MACCtrl0 and MACCtrl1 registers are used to
configure parameters including full duplex, flow
control, and statistics gathering.
In half duplex mode, the IP100 implements the
CSMA/CD algorithm. If multiple nodes on the same
network attempt to transmit simultaneously, a
collision will occur resulting in re-transmission. In full
duplex mode, the IP100 can transmit and receive
frames simultaneously without incurring collisions.
To configure the IP100 for full duplex mode
operation, the host system must detect a full duplex
physical link via the PHY Status Register, and must
set the FullDuplexEnable bit in the MACCtrl0
register.
IP100-DS-R03
May 27, 2003
11/92
Copyright
2003, IC Plus Corp.
All rights reserved.
The IEEE 802.3x Full Duplex standard defines a
special frame known as the PAUSE MAC Control
frame. The PAUSE frame is used to implement flow
control in full duplex networks allowing stations on
opposite ends of a full duplex link the ability to inhibit
transmission of data frames for a specified period of
time. The PAUSE frame format is defined as shown
in Figure 3.
DA
SA
TYPE
OPCODE
PAUSE TIME
PAD
FIELD
6
6
2
2
2
42
0x0180C2000001
0x8808
0x0001
LENGTH
(BYTES)
FIGURE 3: PAUSE Frame
Whenever the FlowControlEnable bit in the
MACCtrl0 register is set, the IP100 looks for any
incoming PAUSE frame. If found, the IP100 inhibits
transmission of all data frames for the time specified
in the two-byte pause_time field. The pause_time
field is specified in slot times relative to the current
data rate; one slot time is 51.2 us at 10 Mbps, and
5.12 us at 100 Mbps. The transmission of PAUSE
frames is the responsibility of the host. The MAC
Control frame must be constructed by the host and
placed into the TxFIFO. For end station applications,
host system should only accept PAUSE frames, and
not generate them. Flow control is designed to
originate from network devices such as switches.
6.3
TxDMA and Frame Transmission
bit
in
the
*
represents
any
The TxDMA Logic transfers frame data from the
host system memory to the IP100 based on a linked
list of frame descriptors called TFDs. The host
system creates a list of TFDs in system memory,
where each TFD contains the memory locations of
one or more fragments of a frame as shown in
Figure 4.
Preliminary, Specification subject to change without notice.
相關(guān)PDF資料 |
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| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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