參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 77/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
10.6.14 IoBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x10
Default .......................... 0x00000001
Width ............................ 32 bits
IoBaseAddress is used to define the I/O base address for the IP100. PCI systems requires that the I/O base
address be set as if the system used 32-bit I/O addressing. The upper 25 bits of IoBaseAddress are read/write
accessible, indicating that the IP100 requires 128 bytes of I/O space in the system I/O map.
BIT
BIT NAME
R/W
0
IoBaseAddrInd
R
I/O Base Address Indicator. When IoBaseAddrInd is a logic 1,
IoBaseAddress contains the valid I/O base address for the IP100.
6..1
Reserved
N/A
Reserved for future use.
31..7
IoBaseAddress
R/W
I/O Base Address. IoBaseAddress contains the 25 bit I/O base
address value. The IP100 uses 128 bytes of I/O address space.
10.6.15 LatencyTimer
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0d
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
2..0
Reserved
N/A
Reserved for future use.
7..3
LatencyTimer
R/W
Latency Timer. LatencyTimer indicates, in increments of 8 bus
clocks, the length of time which the IP100 may hold the PCI bus in
the presence of other bus requestors. Whenever the IP100 asserts
the FRAMEN signal, the latency timer is started. When the latency
timer count expires, the IP100 must relinquish the bus as soon as its
GNTN signal has been deasserted.
10.6.16 MaxLat
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3f
Default .......................... 0x0A
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
MaxLat
R
Maximum Latency. MaxLat specifies, in 250 ns increments, how often
the IP100 requires bus access while operating as a bus master. Bits 5
through 1 of the MaxLat value are loaded from the ConfigParm field
within an EEPROM during auto initialization of the IP100.
IP100-DS-R03
May 27, 2003
77/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
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