參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁數(shù)： 72/92頁
文件大小： 2801K
代理商： IP100
IP100
CISPointer identifies the location of the Card Information Structure (CIS). CISPointer contains the offset of CIS in
memory space. CISPointer value is hardwired and can not be changed. Although the CIS is in memory, it is
physically located in the EEPROM. Because the EEPROM access is so slow, the PCI target will issue a Retry for
each new access.
BIT
BIT NAME
R/W
2..0
AddressSpace
Indicator
address within the space indicated. The AddressSpaceOffset is
added to AddressSpaceIndicator to identify the start of the CIS. The
AddressSpaceIndicator value is 0x2, indicating the IP100 only
supports CIS access in the memory pointed to by the PCI Base
Address Register 1.
27..3
AddressSpaceOffset
R
Address Space Offset. AddressSpaceOffset is the offset from the
base address specified by the PCI Base Address Register 1. The
IP100 supports CIS in memory space.
31..28 ROMImageNumber
R
ROM Image Number. ROMImageNumber is 0x0 indicating the IP100
does not support CIS access in the expansion ROM.
10.6.5 ClassCode
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x09
Default .......................... 0x020000
Width ............................ 24 bits
BIT
BIT NAME
R/W
23..0
ClassCode
R
Class Code. ClassCode identifies the general function of the PCI
device. A value of 0x020000 indicates an Ethernet network controller.
10.6.6 ConfigCommand
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x04
Default .......................... 0x0000
Width ............................ 16 bits
ConfigCommand provides control over the adapter’s ability to generate and respond to PCI cycles. When a zero is
written to ConfigCommand, the IP100 is logically disconnected from the PCI bus, except for configuration cycles.
BIT
BIT NAME
R/W
0
IoSpace
R/W
I/O Space. When IoSpace is a logic the IP100 can respond to I/O
space accesses (if the IP100 is in the D0 power state).
1
MemorySpace
R/W
Memory
Space.
AddressDecodeEnable bit in the ExpRomBaseAddress register are
both a logic 1, and if the IP100 is in the D0 power state, the IP100 is
able to decode accesses to an Expansion ROM (if present).
2
BusMaster
R/W
Bus Master. When BusMaster is a logic 1 the IP100 is able to initiate
bus master cycles (if the adapter is in the D0 power state).
Note: If the IP100 is initialized to PCI-X mode, BusMaster is ignored
when initiating Split Completions.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
72/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
R
Address Space Indicator. AddressSpaceIndicator specifies the base
BIT DESCRIPTION
BIT DESCRIPTION
When
MemorySpace,
and
the
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