- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IP100 PCI 10/100M Single Chip Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 49/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
IP100
BIT
1
IP100-DS-R03
May 27, 2003
49/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
HostError
R/W
R/W
BIT DESCRIPTION
Host Error Interrupt. HostError is a logic 1 when a catastrophic error
related to the bus interface occurs. Catastrophic bus interface errors
include PCI target abort and PCI master abort.
A HostError interrupt requires a setting the GlobalReset and DMA bits
of the AsicCtrl register.
Transmit Complete. TxComplete is a logic 1 when a frame whose
TxIndicate bit in the TFD’s TxFrameControl field is a logic 1, has been
successfully transmitted or for any frame that experiences a
transmission error.
A TxComplete interrupt requires writing to TxStatus register to
advance the status queue.
MAC Control Frame Received Interrupt. MACControlFrame is a logic
1 when a MAC Control frame has been received by the IP100.
Receive Complete Interrupt. RxComplete is a logic 1 when one or
more entire frames have been received into the receive FIFO.
RxComplete is automatically acknowledged by the receive DMA logic
as it transfers frames.
Reserved for future use.
Interrupt Requested Interrupt. IntRequested is a logic 1 after the host
system requests an interrupt by setting InterruptRequest bit of the
AsicCtrl register or via the expiration of the Countdown register.
Update Statistics Interrupt. UpdateStats is a logic 1 to indicate that
one or more of the statistics registers is nearing an overflow condition
(typically half of its maximum value). The host system should respond
to an UpdateStats interrupt by reading all of the statistic registers,
thereby acknowledging and clearing UpdateStats bit.
Link Event Interrupt. LinkEvent is a logic 1 to indicate a change in the
state of the Ethernet link.
Transmit DMA Complete Interrupt. TxDMAComplete is a logic 1 to
indicate that a transmit DMA operation has completed, and the
frame’s corresponding TFD had the TxDMAComplete bit in the
TxFrameControl field set to a logic 1.
Receive DMA Complete Interrupt. RxDMAComplete is a logic 1 to
indicate that a frame receive DMA operation has completed.
Reserved for future use.
Modem Interrupt. Reserved/ModemInt is a logic 1 to indicate that the
MINT signal has been asserted.
Reserved for future use.
2
TxComplete
R/W
3
MACControlFrame
R/W
4
RxComplete
R/W
5
6
Reserved
IntRequested
R/W
R/W
7
UpdateStats
R/W
8
LinkEvent
R/W
9
TxDMAComplete
R/W
10
RxDMAComplete
R/W
11
Reserved/
ModemInt
N/A
R/W
15..12
Reserved
N/A
10.4.17 IntStatusAck
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x4a
Default .......................... 0x0000
Width ............................ 16 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。