參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 73/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
BIT
3
4
IP100-DS-R03
May 27, 2003
73/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
Reserved
MWlEnable
R/W
N/A
R/W
BIT DESCRIPTION
Reserved for future use.
Memory Write and Invalidate Enable. When MWlEnable is a logic 1
the IP100 is permitted to use the MWI command.
Reserved for future use.
Parity Error Response. When ParityErrorResponse is a logic 1 the
IP100 responds to parity errors as defined within the PCI
specification. When ParityErrorResponse is a logic 0, the IP100
ignores parity errors.
Reserved for future use.
System Error Enable. When SERREnable is a logic 1, the SERRN
signal is allowed to transition as appropriate. When SERREnable is
a logic 0, the SERRN signal is a continuous logic 0.
Reserved for future use.
5
6
Reserved
ParityErrorResponse
N/A
R/W
7
8
Reserved
SERREnable
N/A
R/W
15..9
Reserved
N/A
10.6.7 ConfigStatus
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x06
Default .......................... 0x0210
Width ............................ 16 bits
ConfigStatus is used to record status information for PCI bus events. Read/write bits inConfigStatus can only be
reset, not set, by writing to this register. Bits are reset by writing a one to the corresponding bit.
BIT
BIT NAME
R/W
3..0
Reserved
N/A
Reserved for future use.
4
Capabilities
R
Capabilities. Capabilities is a logic 1 to indicate a set of extended
capabilities registers exists for the IP100. The CapPtr register
indicates the first address location of the extended capabilities
register set.
6..5
Reserved
N/A
Reserved for future use.
7
FastBackToBack
R
Fast Back to Back. When FastBackToBack is a logic 1 the IP100
when operating as a Target, supports fast back-to-back transactions
as defined by the criteria in the section 3.4.2 of the PCI specification.
8
DataParityReported
R/W
Master Data Parity Error. When DataParityReported is a logic 1, the
IP100 when operating as a Master, has detected the PERRN signal
asserted, and the ParityErrorResponse bit in the ConfigCommand
register as a logic 1.
10..9
DevselTiming
R
Device Select Timing. DevselTiming is used to encode the slowest
time with which the IP100 asserts the DEVSELN signal. A value of
0x1 for DevselTiming indicates support for “medium” speed
DEVSELN assertion.
11
SignaledTargetAbort
R/W
Signaled Target Abort. The IP100 sets SignaledTargetAbort to a logic
1 when the IP100 terminates a bus transaction with target-abort.
12
ReceivedTarget-
Abort
logic 1 when, operating as a bus master, a IP100 bus transaction is
terminated with target-abort.
BIT DESCRIPTION
R/W
Received Target Abort. The IP100 sets ReceivedTargetAbort to a
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