參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 9/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
with a 2N2905 PNP transistor based circuit as
shown in Figure 2, the REGIN and REGOUT pins
will regulate the current through the transistor,
providing a stable 2.5 V reference.
VCCH
IP100-DS-R03
May 27, 2003
9/92
Copyright
2003, IC Plus Corp.
All rights reserved.
IP100
REGOUT
IP100
REGIN
VCCL
MMBT2907A
150
33
0.1u
2.0K, 1%
2.2K, 1%
FIGURE 2: External PNP Transistor Based
Regulator Circuit
5.4
PCI Bus Interface
The PCI Bus Interface implements the protocols and
signals needed to operate the IP100 in a PCI bus.
The IP100 can be either a PCI bus master or slave.
The PCI Bus Interface is also responsible for
managing the DMA interfaces and the host
processors
access
to
Arbitration logic within the PCI Bus Interface block
accepts bus requests from the TxDMA Logic and
RxDMA Logic.
The PBI also manages interrupt generation for a
host processor.
5.5
TxDMA Logic
the
IP100
registers.
The IP100 supports a multi-frame, multi-fragment
DMA gather process. Descriptors representing
frames are built and linked in system memory by a
host processor. The TxDMA Logic is responsible for
transferring the multi-fragment frame data from the
host memory into the TxFIFO.
The TxDMA Logic monitors the amount of free
space in the TxFIFO, and uses this value to decide
when to request a TxDMA. A TxDMABurstThresh
register is used to delay the bus request until there
is enough free space in the TxFIFO for a long burst.
To prevent a TxFIFO under run condition the
TxDMA logic forwards an urgent request to the
arbiter, regardless of the TxDMABurstThresh
constraint, when the number of occupied bytes in
the
TxFIFO
drops
below
TxDMAUrgentThresh register.
5.6
TxFIFO
the
value
in
The IP100 uses 2K bytes of transmit data buffer
between the TxDMA Logic and Transmit MAC.
When the TxDMA logic determines there is enough
space available in the TxFIFO, the TxDMA Logic will
move any pending frame data into the TxFIFO. The
TxReleaseThresh register value determines the
amount of data which must be transmitted out of the
TxFIFO before the FIFO memory space occupied by
that data can be released for use by another frame.
A
TxReleaseError
occurs
experiences a collision after the TxFIFO release
threshold has been crossed. The IP100 will not be
able to retransmit this frame from the TxFIFO and
the complete frame must be transferred from the
host system memory to the TxFIFO again by
TxDMA Logic.
5.7
RxDMA Logic
when
a
frame
The IP100 supports a multi-frame, multi-fragment
DMA scatter process. Descriptors representing
frames are built and linked in system memory by the
host processor. The RxDMA Logic is responsible for
transferring the frame data from the RxFIFO to the
host memory.
The RxDMA Logic monitors the number of bytes in
the RxFIFO. After a number of bytes have been
received, the frame is “visible”. A frame is visible if:
The frame being received is determined not to
be a runt, OR
The entire frame has been received
After a frame becomes visible, the RxDMA Logic will
issue a request to the arbiter when the number of
bytes in the RxFIFO is greater than the value in the
RxDMABurstThresh. To prevent receive overruns, a
RxDMA Urgent Request is made when the amount
of free space in the RxFIFO falls below the value in
RxDMAUrgentThresh.
5.8
RxFIFO
The IP100 uses 2K bytes of receive data buffer
between the Receive MAC and RxDMA Logic. The
Preliminary, Specification subject to change without notice.
相關(guān)PDF資料
PDF描述
IP101 PHY 10/100M Single Chip Fast Ethernet Transceiver
IP1060AD Analog IC
IP1060AJ Voltage-Mode SMPS Controller
IP1060AN Analog IC
IP1060BJ Voltage-Mode SMPS Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IP1000A 制造商:IC PLUS 功能描述:IP1000A
IP1000ALF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R01 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R02 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R03 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*