參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 47/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
10.4.13 FunctionPresentState
Class............................. LAN I/O Registers, CardBus Status Change
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x20
Default Value ................ 0x00000000
Width ............................ 32 bits
FunctionPresentState reflects the current state of each condition that can cause a status change event.
This register is disabled when the CardBus bit of AsicCtrl is low.
BIT
BIT NAME
R/W
3..0
Reserved
N/A
Reserved for future use.
4
GWAKE
R
GWAKE. GWAKE reflects the current state of the wakeup events
not represented by the PCMCIA WP (Write Protect), RDY (Ready),
or BVD (Battery Voltage Detect) events. See the PmeStatus bit of
the PowerMgmtCtrl register.
14..5
Reserved
N/A
Reserved for future use.
15
INTR
R
INTR. INTR is the logical OR of all the interrupt causing bits after
having been filtered through the IntEnable register.
31..16
Reserved
N/A
Reserved for future use.
10.4.14 HashTable
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x66, 0x64, 0x62, 0x60
Default .......................... 0x0000000000000000
Width ............................ 64 bits (accessible as 4, 16 bit words)
The host system stores a 64-bit hash table in this register for selectively receiving multicast frames. Setting the
ReceiveMulticastHash bit in ReceiveMode register enables the filtering mechanism.
BIT
BIT NAME
R/W
15..0
HashTableWord0
R/W
The least significant word of the hash table, corresponding to
address 0x60.
31..16
HashTableWord1
R/W
The second least significant word of the hash table, corresponding
to address 0x62.
47..32
HashTableWord2
R/W
The second most significant word of the hash table, corresponding
to address 0x64.
63..48
HashTableWord3
R/W
The most significant word of the hash table, corresponding to
address 0x66.
The IP100 applies a cyclic-redundancy-check (the same CRC used to calculate the frame data FCS) to the
destination address of all incoming multicast frames (with multicast bit set). The low-order 6 bits of the CRC result
are used as an addressing index into the hash table. The MSB of HashTable[3] is the most significant bit, and the
LSB of HashTable[0] is the least significant bit, addressed by the 6-bit index. If the HashTable bit addressed by
the index is a logic 1, the frame is accepted by the IP100 and transferred to higher layers. If the addressed hash
table bit is a logic 0, the frame is discarded.
IP100-DS-R03
May 27, 2003
47/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT DESCRIPTION
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